Fault tolerant hypercube computer system architecture

A fault-tolerant multiprocessor computer system of the hypercube type comprising a hierarchy of computers of like kind which can be functionally substituted for one another as necessary is disclosed. Communication between the working nodes is via one communications network while communications between the working nodes and watch dog nodes and load balancing nodes higher in the structure is via another communications network separate from the first. A typical branch of the hierarchy reporting to a master node or host computer comprises, a plurality of first computing nodes; a first network of message conducting paths for interconnecting the first computing nodes as a hypercube. The first network provides a path for message transfer between the first computing nodes; a first watch dog node; and a second network of message connecting paths for connecting the first computing nodes to the first watch dog node independent from the first network, the second network provides an independent path for test message and reconfiguration affecting transfers between the first computing nodes and the first switch watch dog node. There is additionally, a plurality of second computing nodes; a third network of message conducting paths for interconnecting the second computing nodes as a hypercube. The third network provides a path for message transfer between the second computing nodes; a fourth network of message conducting paths for connecting the second computing nodes to the first watch dog node independent from the third network. The fourth network provides an independent path for test message and reconfiguration affecting transfers between the second computing nodes and the first watch dog node; and a first multiplexer disposed between the first watch dog node and the second and fourth networks for allowing the first watch dog node to selectively communicate with individual ones of the computing nodes through the second and fourth networks; as well as, a second watch dog node operably connected to the first multiplexer whereby the second watch dog node can selectively communicate with individual ones of the computing nodes through the second and fourth networks. The branch is completed by a first load balancing node; and a second multiplexer connected between the first load balancing node and the first and second watch dog nodes, allowing the first load balancing node to selectively communicate with the first and second watch dog nodes

EDUCATIONAL PROCESSOR

This report discusses the overview of the chosen project, which is an Educational Processor. The objective of this project is to develop a simple processor with TTL logic for educational purpose. This processor will be used as a learning tool for Computer System Architecture class. To complete this project, the scope of study will cover the computer system architecture and Central Processing Unit (CPU). The CPU datapath design and hardware circuit design is based on the MIPS single-cycle processor. The methodologies that will be involved in this project are design and validation phase, constructing the hardware and then interfacing phase through serial communication between CPU and a graphic user interface using microcontroller. The prototype would be used as a learning tool in Computer System Architecture class and to assist student in understanding the computer architecture

EDUCATIONAL PROCESSOR

This report discusses about the overview of the chosen project, which is an Educational Processor (EduCPU). The objective of this project is to develop a simple processor using TTL logic gates and also to develop simulation software for educational purpose. The software is responsible for sending instruction codes to the simple processor through serial communication in order to execute the instruction. The software written is also capable of simulating the behaviour of the simple processor. This educational processor would be used as a learning tool in Computer System Architecture course in in Universiti Teknologi PETRONAS (UTP) to assist students in understanding about computer system architecture. In order to complete this project, the scope of study basically will cover the computer system architecture and details about Central Processing Unit (CPU). The instruction format and CPU data path design both are based on MIPS architecture processor. The methodologies that are involved in this project are design and validation phase, constructing the hardware, and programming the user interface to interact with the educational processor

An Overview of Chip Multi-Processors Simulators Technology

Computer System Architecture (CSA) simulators are generally used to develop and validate new CSA designs and developments. The goal of this paper is to provide an insight into the importance of CSA simulation and the possible criteria that differentiate between various CSA simulators. Multi-dimensional aspects determine the taxonomy of CSA simulators including their accuracy, performance, functionality and flexibility. The Sniper simulator has been selected for a closer look and testing. The Sniper proofs its ability to scale to hundred cores with a wide range of functionality and performance. © Springer International Publishing Switzerland 2015

Prospects for the Application of Nanotechnologies to the Computer System Architecture

Computer system architecture essentially influences the comfort of our everyday living. Developmental transition from electromechanical relays to vacuum tubes, from transistors to integrated circuits has significantly changed technological standards for the architecture of computer systems. Contemporary information technologies offer huge potential concerning miniaturization of electronic circuits. Presently, a modern integrated circuit includes over a billion of transistors, each of them smaller than 100 nm . Stepping beyond the symbolic 100 nm limit means that with the onset of the 21 century we have entered a new scientific area that is an era of nanotechnologies. Along with the reduction of transistor dimensions their operation speed and efficiency grow. However, the hitherto observed developmental path of classical electronics with its focus on the miniaturization of transistors and memory cells seems arriving at the limits of technological possibilities because of technical problems as well as physical limitations related to the appearance of new nano-scale phenomena as e.g. quantum effects. When you are citing the document, use the following link http://essuir.sumdu.edu.ua/handle/123456789/2488

Prospects for the Application of Nanotechnologies to the Computer System Architecture

Computer system architecture essentially influences the comfort of our everyday living. Developmental transition from electromechanical relays to vacuum tubes, from transistors to integrated circuits has significantly changed technological standards for the architecture of computer systems. Contemporary information technologies offer huge potential concerning miniaturization of electronic circuits. Presently, a modern integrated circuit includes over a billion of transistors, each of them smaller than 100 nm . Stepping beyond the symbolic 100 nm limit means that with the onset of the 21 century we have entered a new scientific area that is an era of nanotechnologies. Along with the reduction of transistor dimensions their operation speed and efficiency grow. However, the hitherto observed developmental path of classical electronics with its focus on the miniaturization of transistors and memory cells seems arriving at the limits of technological possibilities because of technical problems as well as physical limitations related to the appearance of new nano-scale phenomena as e.g. quantum effects. When you are citing the document, use the following link http://essuir.sumdu.edu.ua/handle/123456789/2488

Advanced information processing system for advanced launch system: Avionics architecture synthesis

The Advanced Information Processing System (AIPS) is a fault-tolerant distributed computer system architecture that was developed to meet the real time computational needs of advanced aerospace vehicles. One such vehicle is the Advanced Launch System (ALS) being developed jointly by NASA and the Department of Defense to launch heavy payloads into low earth orbit at one tenth the cost (per pound of payload) of the current launch vehicles. An avionics architecture that utilizes the AIPS hardware and software building blocks was synthesized for ALS. The AIPS for ALS architecture synthesis process starting with the ALS mission requirements and ending with an analysis of the candidate ALS avionics architecture is described

Flight design system requirements evaluation program

Flight planning requirements were analyzed and a computer system architecture was defined. An evaluation method of the proposed flight design system is also included

Integrated Continuous Healthcare Team Computer System Architecture

A computer-based pattern recognition system architecture destined to collect and process geographically referenced data about integrated continuous healthcare teams (ECCI) is presented and discussed in the chapter. These teams are part of Portugal's National Network of Integrated Continuous Care (RNCCI). The system is designed to collect data about the displacement of each team during healthcare assistance. The pattern recognition system handles information about the costs related to the provided healthcare. The architecture is designed around open source software resources. Virtual machines and container-based technologies provide hardware independence. The Python programming language ecosystem is chosen for all the main components of the s

VLSI Multiple Microcomputer Technology Applied to Real-Time Simulators

VLSI technology, embodied in state of the art microprocessors and microcomputers, has implied a computer system architecture that offers the possibility for extensive standardization, modularity, and performance improvements that can significantly impact and reduce the lifetime costs of real-time simulators. This report discusses one such system. Both the hardware and software aspects of the system are examined