A methodology for exploiting parallelism in the finite element process

A methodology is described for developing a parallel system using a top down approach taking into account the requirements of the user. Substructuring, a popular technique in structural analysis, is used to illustrate this approach

Information fusion based techniques for HEVC

Aiming at the conflict circumstances of multi-parameter H.265/HEVC encoder system, the present paper introduces the analysis of many optimizations\u27 set in order to improve the trade-off between quality, performance and power consumption for different reliable and accurate applications. This method is based on the Pareto optimization and has been tested with different resolutions on real-time encoders

A Domain Independent Framework for Developing Knowledge Based Computer Generated Forces

Computer Generated Forces (CGFs) are important players in Distributed Interactive Simulation (DIS) exercises. A problem with CGFs is that they do not exhibit sufficient human behaviors to make their use effective. The SOAR approach has yielded a human cognitive model that can be applied to CGFs, but this is extremely complex. The product of the research reported in this thesis is a much less complex behavioral framework for a CGF that is easy to validate, revise, and maintain. To support this, an existing, domain independent CGF architecture is discussed and applied to an experimental CGF. Techniques for modeling the knowledge and behaviors of any CGF via semantic nets are presented. A process for transforming the semantic nets into fuzzy controllers is outlined, and pertinent issues regarding fuzzy controllers are discussed. Lastly, a method for making time critical decisions via fuzzy logic is presented

Breadth-First Search on a MapReduce One-Chip System

An implementation of a newly developed parallel graph traversal algorithm on a new one-chip many-core structure with a MapReduce architecture is presented. The generic structure's main features and performances are described. The developed algorithm uses the representation of the graph as a matrix and the new MapReduce structure performs best on matrix-vector operations so, the algorithm considers both, dense and sparse matrix cases. A Verilog based simulator is used for evaluation. The main outcome of the presented research is that our MapReduce architecture (with P execution units and the size in O(P)) has the same theoretical time performance: O(NlogN) for P = N = |V | = number of vertices in the graph, as the hypercube architecture (having P processors and the size in O(PlogP)). Also, the actual energy performance of our architecture is 7 pJ for 32-bit integer operation, compared with the ~150pJ per operation of the current many-cores

Vertical motion simulator familiarization guide

The Vertical Motion Simulator Familiarization Guide provides a synoptic description of the Vertical Motion Simulator (VMS) and descriptions of the various simulation components and systems. The intended audience is the community of scientists and engineers who employ the VMS for research and development. The concept of a research simulator system is introduced and the building block nature of the VMS is emphasized. Individual sections describe all the hardware elements in terms of general properties and capabilities. Also included are an example of a typical VMS simulation which graphically illustrates the composition of the system and shows the signal flow among the elements and a glossary of specialized terms, abbreviations, and acronyms

Design and implementation of a fast Fourier transform architecture using twiddle factor based decomposition algorithm

With the advent of signal processing and wireless communication mobile platform devices, the necessity for data transformation from one form to another becomes an unavoidable aspect. One such mathematical tool that is widely used for transforming time and frequency domain signals is Fourier Transform. Fast Fourier Transform (FFT) is perhaps the fastest way to achieve transformation. Many algorithms and architectures have been designed over the years in an attempt to make FFT algorithms more efficient and to target many applications; The main objective of our work is to design, simulate and implement an architecture based on the Twiddle-Factor-Based decomposition FFT algorithm. The significant feature of the algorithm is its effective memory access reduction that accounts to be as much as 30% lesser than in any other conventional FFT algorithms. As a result of this memory reduction, this algorithm is said to be more power efficient and is said to compute in much lesser number of clock cycles than other algorithms developed; The real focus of the design is to build architecture to map this efficient algorithm on to hardware retaining the maximum efficiency of the algorithm. The complete design, simulation and testing is done using Active-HDL tool which is a VHDL package designed. The architecture designed is found to retain the memory savings capability of the algorithm thus enabling power efficiency

Visual Programming: Concepts and Implementations

The computing environment has changed dramatically since the advent of the computer. Enhanced computer graphics and sheer processing power have ushered in a new age of computing. User interfaces have advanced from simple line entry to powerful graphical interfaces. With these advances, computer languages are no longer forced to be sequentially and textually-based. A new programming paradigm has evolved to harness the power of today's computing environment - visual programming. Visual programming provides the user with visible models which reflect physical objects. By connecting these visible models to each other, an executable program is created. By removing the inherent abstractions of textual languages, visual programming could lead computing into a new era

Performance Evaluation of Orthogonal Frequency Division Multiplexing using 16-bit Irregular Data Formats

This report asserts that 16-bit Digital Signal Processing applications suffer from dynamic range and noise performance issues. This problem is highly common in complex DSP algorithms and is compounded if they are programmed in high level languages due to no native compiler support for 16-bit data formats. A solution to this problem is achieved by using 16-bit irregular data formats which show significant improvement over fixed and floating point approaches. First, the data formatting problem for 16-bit programmable devices are defined and discussed. Existing solutions to the problem is taken into consideration. Then a new class of floating point numbers is obtained from which irregular data formats are derived. Attempts are made to derive format with greater dynamic range and noise performance. Then the irregular data format along with fixed and floating point formats are simulated and analysed for simple DSP applications to make a performance analysis. Finally the data formats under consideration are implemented in a full-fledged Orthogonal Frequency Division Multiplexing model. The inputs and outputs obtained are compared for the percentage of error and final conclusions are drawn. The results indicate that irregular data formats have significant improvement over fixed and floating point formats and 16-bit DSP applications can be implemented in a more effective way using irregular data formats