Redesigning Commercial Floating-Gate Memory for Analog Computing Applications

We have modified a commercial NOR flash memory array to enable high-precision tuning of individual floating-gate cells for analog computing applications. The modified array area per cell in a 180 nm process is about 1.5 um^2. While this area is approximately twice the original cell size, it is still at least an order of magnitude smaller than in the state-of-the-art analog circuit implementations. The new memory cell arrays have been successfully tested, in particular confirming that each cell may be automatically tuned, with ~1% precision, to any desired subthreshold readout current value within an almost three-orders-of-magnitude dynamic range, even using an unoptimized tuning algorithm. Preliminary results for a four-quadrant vector-by-matrix multiplier, implemented with the modified memory array gate-coupled with additional peripheral floating-gate transistors, show highly linear transfer characteristics over a broad range of input currents.Comment: 4 pages, 6 figure

A Comprehensive Simulation Model for Floating Gate Transistors

Floating-gate transistors have proven to be extremely useful devices in the development of analog systems; however, the inability to properly simulate these devices has held back their adoption. The objective of this work was to develop a complete simulation model for a floating-gate (FG) MOSFET using both standard SPICE primitives and also MOSFET models taken directly from foundry characterizations. This new simulation model will give analog designers the ability simulate all aspects of floating-gate device operation including transient, AC and DC characteristics. This work describes the development of this model and demonstrates its use in various applications

Competitive Learning With Floating-Gate Circuits

Competitive learning is a general technique for training clustering and classification networks. We have developed an 11-transistor silicon circuit, that we term an automaximizing bump circuit, that uses silicon physics to naturally implement a similarity computation, local adaptation, simultaneous adaptation and computation and nonvolatile storage. This circuit is an ideal building block for constructing competitive-learning networks. We illustrate the adaptive nature of the automaximizing bump in two ways. First, we demonstrate a silicon competitive-learning circuit that clusters one-dimensional (1-D) data. We then illustrate a general architecture based on the automaximizing bump circuit; we show the effectiveness of this architecture, via software simulation, on a general clustering task. We corroborate our analysis with experimental data from circuits fabricated in a 0.35-µm CMOS process