Study of Novel Power Semiconductor Devices for Performance and Reliability.

Power Semiconductor Devices are crucial components in present day power electronic systems. The performance and efficiency of the devices have a direct correlation with the power system efficiency. This dissertation will examine some of the components that are commonly used in a power system, with emphasis on their performance characteristics and reliability. In recent times, there has a proliferation of charge balance devices in high voltage discrete power devices. We examine the same charge balance concept in a fast recovery diode and a MOSFET. This is crucial in the extending system performance at compact dimensions. At smaller device and system sizes, the performance trade-off between the ON and OFF states becomes all the more critical. The focus on reducing the switching losses while maintaining system reliability increases. In a conventional planar technology, the technology places a limit on the switching performance owing to the larger die sizes. Using a charge balance structure helps achieve the improved trade-off, while working towards ultimately improving system reliability, size and cost. Chapter 1 introduces the basic power system based on an inductive switching circuit, and the various components that determine its efficiency. Chapter 2 presents a novel Trench Fast Recovery Diode (FRD) structure with injection control is proposed in this dissertation. The proposed structure achieves improved carrier profile without the need for excess lifetime control. This substantially improves the device performance, especially at extreme temperatures (-40oC to 175oC). The device maintains low leakage at high temperatures, and it\u27s Qrr and Irm do not degrade as is the usual case in heavily electron radiated devices. A 1600 diode using this structure has been developed, with a low forward turn-on voltage and good reverse recovery properties. The experimental results show that the structure maintains its performance at high temperatures. In chapter 3, we develop a termination scheme for the previously mentioned diode. A major limitation on the performance of high voltage power semiconductor is the edge termination of the device. It is critical to maintain the breakdown voltage of the device without compromising the reliability of the device by controlling the surface electric field. A good termination structure is critical to the reliability of the power semiconductor device. The proposed termination uses a novel trench MOS with buried guard ring structure to completely eliminate high surface electric field in the silicon region of the termination. The termination scheme was applied towards a 1350 V fast recovery diode, and showed excellent results. It achieved 98% of parallel plane breakdown voltage, with low leakage and no shifts after High Temperature Reverse Bias testing due to mobile ion contamination from packaging mold compound. In chapter 4, we also investigate the device physics behind a superjunction MOSFET structure for improved robustness. The biggest issue with a completely charge balanced MOSFET is decreased robustness in an Unclamped Inductive Switching (UIS) Circuit. The equally charged P and N pillars result in a flat electric field profile, with the peak carrier density closer to the P-N junction at the surface. This results in an almost negligible positive dynamic Rds-on effect in the MOSFET. By changing the charge profile of the P-column, either by increasing it completely or by implementing a graded profile with the heavier P on top, we can change the field profile and shift the carrier density deeper into silicon, increasing the positive dynamic Rds-on effect. Simulation and experimental results are presented to support the theory and understanding. Chapter 5 summarizes all the theories presented and the contributions made by them in the field. It also seeks to highlight future work to be done in these areas

Simulation study of silicon carbide Clustered Insulated Gate Bipolar Transistor (CIGBT)

Power semiconductor devices are inevitable parts of a power electronic converter system, with nearly 50% of electricity used in the world controlled by them. Silicon power devices have been used in power systems ever since the vacuum tubes were replaced by them in the 1950s. The performance of devices in a circuit is decided by the switching strategies and the inherent device performance like its on-state voltage, turn-on and turn-off times and hence their losses. Due to their inherent material properties, the growing interest in wide band gap devices is in applications beyond the limits of Si or GaAs. SiC is a wide bandgap material with properties that make it an attractive alternative to Silicon for high power applications. Silicon Insulated Gate Bipolar Transistor (IGBT) is the most favourable device in the industry today for medium/high power applications. Silicon Clustered Insulated Gate Bipolar Transistor (CIGBT) is experimentally proven to demonstrate better performance as compared to their IGBT counterparts. In this work, the theoretical limit of silicon CIGBT is studied in great detail and compared to previously predicted IGBT limit. Later part of this thesis would explain the design and optimization of CIGBT in 4H- SiC. An in-depth simulation study of the same device is performed for both static and dynamic characteristics. Both planar and trench gate CIGBT devices are discussed here along with possible fabrication process. Along with this, a comparison study between CIGBT with its equivalent IGBT in SiC is also performed through extensive 2D simulations in MEDICITM in terms of their static and dynamic characteristics. Finally, a comparative study of P channel and N channel SiC CIGBT devices is evaluated through simulations

Gestion thermique des composants d'électronique de puissance - Utilisation du diamant CVD

L'augmentation de la densité de puissance des convertisseurs d'énergie électrique nécessite une gestion thermique toujours plus performante. La thermique devient même l'élément dimensionnant de ces convertisseurs et est au centre des préoccupations des concepteurs. Le diamant présente des propriétés physico-chimiques exceptionnelles particulièrement adaptées à la gestion thermique des composants semi-conducteurs de l'électronique de puissance. C'est en effet le meilleur matériau isolant et conducteur thermique connu à ce jour. La possibilité de réaliser du diamant polycristallin de manière reproductible par synthèse CVD ouvre aujourd'hui à ce matériau un grand champ d'applications industrielles. Nous avons étudié les potentialités d'applications au domaine particulier de l'électronique de puissance. Nous avons tout d'abord développé une plateforme de simulation COMSOL qui nous permette d'évaluer différentes structures pour optimiser le système de refroidissement des composants d'électronique de puissance. Nous avons alors étudié deux solutions, l'utilisation d'un substrat diamant épais pour reporter les composants ou le dépôt direct d'une fine couche de passivation sur les composants en fin de fabrication. Nous avons ainsi développé une structure à substrat diamant et micropoteaux en cuivre qui permet d'extraire jusqu'à 800 W/cm sous le composant pour un échauffement de 120C. Cette structure a été réalisée technologiquement pour valider toute la démarche de simulation et conception. Ce prototype propose des performances particulièrement intéressantes pour l'intégration des convertisseurs d'électronique de puissance à haute densité de puissance. Nous avons également étudié la passivation des composants avec du diamant CVD en lieu et place du SiO2. L'intérêt d'une telle passivation est démontré en simulation et les différentes étapes de la réalisation technologique sont étudiées. Cette dernière partie met en évidence des difficultés qu'il faudra lever si l'on souhaite utiliser le diamant comme couche de passivationThe heat transfer is a major obstacle that limits the generalization of the power electronics. During recent years, components have higher performance and smaller size thanks to technological advances in electronic. However, the maximum operation temperature of silicon components has not changed for years. A lot of problems will appear due to the thermal limitation. Thus, electronic circuit design must be accompanied by a thermal study to validate the safe operation. The diamond has outstanding properties. It has several exceptional physical and chemical characteristics. This material is very interesting in plenty of application domains, such as electronics, mechanics, optics and telecommunications. This is the best material for electrical insulators (10MV.cm-1) and thermal conductors (2000W.m-1.K-1, five times more than copper). Nevertheless, the coefficient of thermal expansion of diamond is very close to that of silicon. These properties are particularly interesting in elaborating highly efficient thermal management systems in power electronics domain. In this study, we analyzed and quantified the advantages of the insertion of CVD diamond layer in the innovative thermal management assemblies. We also developed a specific model (We increased a layer of copper micro-pillars on the backside of the diamond substrate) to simulate the working environment of the component. In the simulation, we compared the use of a traditional substrate (AlN) with that of the diamond CVD one in order to confirm that using the diamond substrate reduced thermal resistance. By using MEMS micro-technology, the cooling performance of this structure has been greatly improved. This structure can achieve power dissipation more than 800W/cm . Using CVD diamond for efficient cooling of power devices could be a promising solution and is very interesting in embedded systems. This achievement in temperature range allows designers to increase the power density of system without concerning of heat dissipation and/or greatly extends the lifetime of the device. We also studied the passivation with CVD diamond instead of SiO2TOULOUSE-INP (315552154) / SudocSudocFranceF

Characterization Methodology, Modeling, and Converter Design for 600 V Enhancement-Mode GaN FETs

Gallium Nitride (GaN) power devices are an emerging technology that have only become available commercially in the past few years. This new technology enables the design of converters at higher frequencies and efficiencies than those achievable with conventional Si devices. This dissertation reviews the unique characteristics, commercial status, and design challenges that surround GaN FETs, in order to provide sufficient background to potential GaN-based converter designers.Methodology for experimentally characterizing a GaN FET was also presented, including static characterization with a curve tracer and impedance analyzer, as well as dynamic characterization in a double pulse test setup. This methodology was supplemented by additional tests to determine losses caused by Miller-induced cross talk, and the tradeoff between these losses and overlap losses was studied for one example device.Based on analysis of characterization results, a simplified model was developed to describe the overall switching behavior and some unique features of the device. The impact of the Miller effect during the turn-on transient was studied, as well as the dynamic performance of GaN at elevated temperature.Furthermore, solutions were proposed for several key design challenges in GaN-based converters. First, a driver-integrated overcurrent and short-circuit protection scheme was developed, based on the relationship between gate voltage and drain current in GaN gate injection transistors. Second, the limitations on maximum utilization of current and voltage in a GaN FET were studied, particularly the voltage overshoots following turn-on and turn-off switching transients, and the effective cooling of GaN FETs in higher power operation. A thermal design was developed for heat extraction from bottom-cooled surface-mount devices. These solutions were verified in a GaN-based full-bridge single-phase inverter

High Efficiency IGBTs through Novel Three-Dimensional Modelling and New Architectures

New Insulated Gate Bipolar Transistor (IGBT) designs are reliant on simulation tools, such as Sentaurus technology computer-aided design (TCAD) models, which allow for rapid device development that could not be achieved by manufacturing prototypes due to the cost and time associated with fabrication. These simulations are, though, computationally expensive and typically most design engineers develop these TCAD models only in two dimensions. This leads to inaccuracies in the model output since manufactured transistors are inherently three-dimensional (3D). Based upon a commercial IGBT, this thesis begins by outlining the development of a 3D TCAD model using design details provided by the manufacturer. Large variations between the experimental data from the manufactured device and the simulation model lead to the discovery of widespread birds-beaking within the IGBT – an uncontrollable processing defect that the manufacturer was unaware of. This thesis presents a new simulation technique to account for this processing error while minimising computational effort and investigates the consequence of this birds-beak on the reliability of the device. The verified 3D IGBT model was also used to determine an optimum cell design that considered critical 3D effects omitted from previous studies. An extensive literature review for the Reverse-Conducting IGBT (RC-IGBT) is provided. It is shown that despite the benefits of the RC-IGBT, the device suffers from many undesirable design trade-offs that have prevented its widespread use. The RC-IGBT designs that have currently been proposed in literature, either present a trade-off in performance, an inability to be manufactured, or a requirement for a custom gate drive. This thesis presents a new RC-IGBT concept, the ‘Dual Implant SuperJunction (SJ) RC-IGBT’ that addresses these concerns and is manufacturable using current state of the art techniques. The concept and proposed manufacturing method enables, for the first time, a full SuperJunction structure to be achieved in a 1.2kV device. In addition, an investigation into a coordinated switching scheme using both a silicon IGBT and silicon-carbide MOSFET was undertaken, which aimed to improve turn-off losses within the IGBT without sacrificing on-state losses. Thermal modelling of the power devices switching under inductive load was explored as the system was optimised to use a SiC MOSFET in excess of its nominal ratings, reducing the overall system cost.EPSRC Doctoral Training Partnership scheme (grant RG75686

Architectures d'intégration mixte monolithique-hybride de cellules de commutation de puissance sur puces multi-pôles silicium et assemblages optimisés

Actuellement, le module de puissance (convertisseur de puissance) standard hybride 2D est la technologie de référence qui domine le marché de la moyenne et de la forte puissance. Ce dernier se présente sous la forme d'un boitier à multi-puces discrètes. Les puces à semi-conducteur sont reliées entre elles par des faisceaux de wire-bonding (câblage par fils) pour former des cellules de commutation. La technologie d'interconnexion wire-bonding présente une grande maturité technologique, et ses modes de défaillance sont bien connus aujourd'hui. Toutefois, cette technologie est un facteur limitant en termes de performances électrique et thermomécanique, d'intégrabilité tridimensionnelle et de productivité. Ces travaux de thèse ont pour objectif de proposer et d'étudier de nouvelles architectures de convertisseurs de puissance très intégrés. Comparée à la technologie hybride, dite de référence, les architectures proposées visent à un degré d'intégration plus poussé, avec un effort d'intégration partagé et conjoint au niveau semi-conducteur (intégration monolithique) et au niveau assemblage (intégration hybride). L'intégration monolithique consiste à intégrer les interrupteurs formant les cellules de commutation dans de nouvelles architectures de puces, passant ainsi de la notion de puce dipôle à celle de macro-puce multi-pôle. L'intégration hybride repose sur le développement de nouvelles technologies de report et d'assemblage de ces macro-puces. Pour valider les trois nouvelles architectures d'intégrations proposées, la démarche a consisté dans un premier temps à étudier et valider le fonctionnement des nouvelles puces par des simulations SentaurusTM TCAD. Ensuite, les puces multi-pôles ont été réalisées en s'appuyant sur la filière IGBT disponible dans la plateforme de micro-fabrication du LAAS-CNRS. Pour finir, les puces ont été reportées sur des cartes PCB, afin de réaliser des circuits de conversions prototypes. La maille de commutation très intégrée proposée présente une inductance parasite inférieure au nanohenry, ce qui est remarquable comparée à ce qui est présenté dans l'état de l'art (env. 20 nH).Currently, the standard 2D hybrid power module (power converter) is the reference technology for the medium and high power market. This hybrid power module is a discrete multi-chip case. The semi-conductor chips are interconnected by wire-bonding to form switching cells. The wire-bonding interconnection technology is a limiting factor in terms of electrical and thermomechanical performances, three-dimensional integrability and productivity. The aim of this thesis is to study new architectures of very integrated power converters. Compared to the so-called hybrid reference technology, the proposed architectures aim at a greater degree of integration, with an integration at both the semi-conductor level (monolithic integration) and the packaging level (hybrid integration). Monolithic integration consists in integrating switching cells into new multi-terminal macro-chip architectures. Hybrid integration consists in developing of new technologies to assemble these macro-chips. To validate the different proposed integration architectures, the first step was to study and validate the operating modes of the new chips by SentaurusTM TCAD simulations. Then, the multi-terminal chips were realized in the micro and nanotechnology platform of LAAS-CNRS laboratory. Finally, the chips were bonded on PCB substrates to realize power converter circuit prototypes. The highly integrated switching loop presents a stray inductance loop lower than one nanohenry, wich is an important improvement as compared to the values reported in literature (about 20 nH)

Investigation of Threshold Voltage Instability in Normally Off GaN on Si HEMT

Wide bandgap semiconductor by virtue of its high critical electric field, low intrinsic carrier concentration, high thermal conductivity is considered a promising material for enabling high density power conversion systems with a smaller form factor. Gallium Nitride (GaN) in particular, with its ability to form heterointerfaces naturally forms a high mobility 2-dimensional electron gas (2-DEG) at hetero interfaces like AlGaN/GaN making it an apt candidate for making power devices with lower on state resistance and higher frequency of operation. With the recent advances in epitaxial growth of GaN on Silicon (Si) substrates, AlGaN/GaN on Si High Electron Mobility Transistors (HEMT) have gained unprecedented commercial attention. Normally off HEMT devices are essential to design robust power systems. Of the various normally off HEMT architectures p- GaN HEMT has significant traction. Despite the advancements, reliability of HEMTs remains a challenge. Significant work has been done in the recent few years to mitigate reliability issues like Dynamic on resistance (D-RON), by continuously improving the quality of the GaN buffer and transition layers. However, threshold voltage instability exists as a key reliability issue which is not well understood. In this thesis, we investigate on threshold voltage instability of normally off 600-650V p-GaN AlGaN/GaN on Si HEMT. This thesis aims to advance the physical understanding of the threshold voltage (VTH) instability arising during the VTH measurement, nominal ON state and OFF state stresses by novel measurement techniques and a comprehensive TCAD modelling. This thesis starts by analytically understanding the design parameters across the gate stack which have a significant control on the threshold voltage (VTH). The measurement induced VTH instability is quantified for the first time and the best practices to mitigate them are proposed. Physical models explaining the instability mechanism are proposed and validated using detailed TCAD simulations. The effect of Schottky gate and ohmic gate contacts on the VTH instability and the challenges in making reliable measurements of VTH are summarised. Subsequently the nominal ON state, OFF state stress induced effect on threshold voltage is studied in detail. It has been shown that OFF state stress voltages (600V) at the drain terminal creates a dynamic threshold voltage in addition to creating a D-RON. The physical mechanisms behind the OFF-state stress induced dynamic threshold voltage are proposed and validated using TCAD simulations. Threshold voltage is a key parameter for the designer to design power systems and its instability is a crucial issue. The implications of the VTH instability at the system level are reviewed and a technique to extract the recovery time of the threshold voltage, post instability is developed. This thesis investigates and advances the science around the threshold voltage instability of the normally off p-GaN AlGaN /GaN on Si HEMT. In summary, this work has quantified the measurement induced VTH instability and addressed the challenges of the VTH measurement in the Ohmic/Schottky type p-GaN gate with detailed TCAD analysis. This work also demonstrates the existence of the OFF-state stress induced dynamic threshold voltage with TCAD validated physical models. In addition to the above this work also showcases a novel measurement technique to extract the recovery time post threshold voltage instability

Conception d'une nouvelle génération de transistor FLYMOS vertical de puissance dépassant la limite conventionnelle du silicium

Dans un contexte énergétique mondial difficile, l'amélioration de la gestion de l'énergie électrique revêt une importance majeure. Le transfert de cette énergie électrique est assuré par l'intermédiaire de systèmes de puissances intégrant majoritairement des composants semi-conducteurs de puissance. La démarche d'optimisation entreprise depuis plusieurs années s'est concentrée sur la réduction des pertes en conduction. Dans ce cadre, les performances des transistors MOSFET sont exprimées par le compromis " tenue en tension (BVdss) / résistance à l'état passant (RON.S) ". Pour améliorer ce compromis, des concepts innovants telles que les Superjonctions ou les îlots flottants ont été développées sur silicium, permettant notamment de réduire drastiquement la résistance à l'état passant. Les travaux de recherche présentés dans cette thèse portent sur la réalisation d'un transistor FLYMOS intégrant jusqu'à deux niveaux d'îlots flottants de type P dans la région épitaxiée N-. Pour la première fois, la forme et les dimensions des îlots flottants ont été déterminées à l'aide d'une caractérisation physique originale. De plus, les limites du FLYMOS ont pu être définies à l'aide de caractérisations électriques dynamiques. Grâce à ces premières études, la compréhension phénoménologique de fonctionnement de ce type de composant a permis le développement d'un processus d'optimisation. Ainsi, des transistors FLYMOS d'une tenue en tension de 230 V ont été réalisés avec succès et leur résistance spécifique à l'état passant de 4,5 m[omega].cm2 se révèle inférieure à la limite conventionnelle du silicium. Au final, la caractérisation électrique complète de ces composants a permis de montrer qu'ils étaient une bonne alternative aux composants 200 V à Superjonction.In a difficult worldwide energy environment, the improvement of electrical energy management is very key. The transfer of this electric energy is provided through power systems integrating principally power semiconductors devices. Since many years, the optimization process has focused on the reduction of conduction losses. In this context, the power MOSFET transistors performances are expressed through the "breakdown voltage (BVdss) / specific on-resistance (RON.S)" trade-off. To improve it, innovative concepts such as Superjonctions or Floating Islands have been developed and, as a result, have drastically reduced the on-resistance. The research presented in this thesis focused on the achievement of FLYMOS transistors incorporating up to two levels of P-type floating islands in the N- epitaxial region. For the first time, the shape and size of the floating islands were determined with an original physical characterization. In addition, the FLYMOS boundaries have been defined using electric dynamic characterizations. Thanks to these first studies, phenomenological understanding of this kind of component has allowed the development of an optimization process. Thus, FLYMOS transistors sustaining voltage of 230 V has been successfully developed and their specific on-resistance of 4,5 m[omega].cm2 overcomes the conventional silicon limit. Finally, a complete electrical characterization of these devices allowed to show that there are a good alternative to 200 V Superjunction devices

Journal of Telecommunications and Information Technology, 2000, nr 3,4

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