Accurate simulations of the interplay between process and statistical variability for nanoscale FinFET-based SRAM cell stability

In this paper we illustrate how by using advanced atomistic TCAD tools the interplay between long-range process variation and short-range statistical variability in FinFETs can be accurately modelled and simulated for the purposes of Design-Technology Co-Optimization (DTCO). The proposed statistical simulation and compact modelling methodology is demonstrated via a comprehensive evaluation of the impact of FinFET variability on SRAM cell stability

Impact of self-heating on the statistical variability in bulk and SOI FinFETs

In this paper for the first time we study the impact of self-heating on the statistical variability of bulk and SOI FinFETs designed to meet the requirements of the 14/16nm technology node. The simulations are performed using the GSS ‘atomistic’ simulator GARAND using an enhanced electro-thermal model that takes into account the impact of the fin geometry on the thermal conductivity. In the simulations we have compared the statistical variability obtained from full-scale electro-thermal simulations with the variability at uniform room temperature and at the maximum or average temperatures obtained in the electro-thermal simulations. The combined effects of line edge roughness and metal gate granularity are taken into account. The distributions and the correlations between key figures of merit including the threshold voltage, on-current, subthreshold slope and leakage current are presented and analysed

Modelling and simulation of advanced semiconductor devices

This paper presents a modelling and simulation study of advanced semiconductor devices. Different Technology Computer Aided Design approaches and models, used in nowadays research are described here. Our discussions are based on numerous theoretical approaches starting from first principle methods and continuing with discussions based on more well stablished methods such as Drift-Diffusion, Monte Carlo and Non-Equilibrium Green’s Function formalism

Analog/RF Circuit Design Techniques for Nanometerscale IC Technologies

CMOS evolution introduces several problems in analog design. Gate-leakage mismatch exceeds conventional matching tolerances requiring active cancellation techniques or alternative architectures. One strategy to deal with the use of lower supply voltages is to operate critical parts at higher supply voltages, by exploiting combinations of thin- and thick-oxide transistors. Alternatively, low voltage circuit techniques are successfully developed. In order to benefit from nanometer scale CMOS technology, more functionality is shifted to the digital domain, including parts of the RF circuits. At the same time, analog control for digital and digital control for analog emerges to deal with current and upcoming imperfections

Electrostatic Analysis of Gate All Around (GAA) Nanowire over FinFET

abstract: CMOS Technology has been scaled down to 7 nm with FinFET replacing planar MOSFET devices. Due to short channel effects, the FinFET structure was developed to provide better electrostatic control on subthreshold leakage and saturation current over planar MOSFETs while having the desired current drive. The FinFET structure has an undoped or fully depleted fin, which supports immunity from random dopant fluctuations (RDF – a phenomenon which causes a reduction in the threshold voltage and is prominent at sub 50 nm tech nodes due to lesser dopant atoms) and thus causes threshold voltage (Vth) roll-off by reducing the Vth. However, as the advanced CMOS technologies are shrinking down to a 5 nm technology node, subthreshold leakage and drain-induced-barrier-lowering (DIBL) are driving the introduction of new metal-oxide-semiconductor field-effect transistor (MOSFET) structures to improve performance. GAA field effect transistors are shown to be the potential candidates for these advanced nodes. In nanowire devices, due to the presence of the gate on all sides of the channel, DIBL should be lower compared to the FinFETs. A 3-D technology computer aided design (TCAD) device simulation is done to compare the performance of FinFET and GAA nanowire structures with vertically stacked horizontal nanowires. Subthreshold slope, DIBL & saturation current are measured and compared between these devices. The FinFET’s device performance has been matched with the ASAP7 compact model with the impact of tensile and compressive strain on NMOS & PMOS respectively. Metal work function is adjusted for the desired current drive. The nanowires have shown better electrostatic performance over FinFETs with excellent improvement in DIBL and subthreshold slope. This proves that horizontal nanowires can be the potential candidate for 5 nm technology node. A GAA nanowire structure for 5 nm tech node is characterized with a gate length of 15 nm. The structure is scaled down from 7 nm node to 5 nm by using a scaling factor of 0.7.Dissertation/ThesisMasters Thesis Electrical Engineering 201

Performance Analysis of FinFET Based Inverter circuit, NAND and NOR Gate at 22nm and 14nm Node technologies.

The size of integrated devices such as PC, mobiles etc are reducing day by day with multiple operations, all of these is happening because of the scaling down the size of MOSFETs which is the main component in memory, processors and so on. As we scale down the MOSFETs to the nanometer regime the short channel effects arises which degrades the system performance and reliability. Here in this paper we describe the alternative MOSFET called FinFET which reduces the short channel effects and its performance analysis of digital applications such as inverter circuit, nand and nor gates at 22nm and 14nm node technologies. DOI: 10.17762/ijritcc2321-8169.15050

Nano-scale TG-FinFET: Simulation and Analysis

Transistor has been designed and fabricated in the same way since its invention more than four decades ago enabling exponential shrinking in the channel length. However, hitting fundamental limits imposed the need for introducing disruptive technology to take over. FinFET - 3-D transistor - has been emerged as the first successor to MOSFET to continue the technology scaling roadmap. In this thesis, scaling of nano-meter FinFET has been investigated on both the device and circuit levels. The studies, primarily, consider FinFET in its tri-gate (TG) structure. On the device level, first, the main TCAD models used in simulating electron transport are benchmarked against the most accurate results on the semi-classical level using Monte Carlo techniques. Different models and modifications are investigated in a trial to extend one of the conventional models to the nano-scale simulations. Second, a numerical study for scaling TG-FinFET according to the most recent International Technology Roadmap of Semiconductors is carried out by means of quantum corrected 3-D Monte Carlo simulations in the ballistic and quasi-ballistic regimes, to assess its ultimate performance and scaling behavior for the next generations. Ballisticity ratio (BR) is extracted and discussed over different channel lengths. The electron velocity along the channel is analyzed showing the physical significance of the off-equilibrium transport with scaling the channel length. On the circuit level, first, the impact of FinFET scaling on basic circuit blocks is investigated based on the PTM models. 256-bit (6T) SRAM is evaluated for channel lengths of 20nm down to 7nm showing the scaling trends of basic performance metrics. In addition, the impact of VT variations on the delay, power, and stability is reported considering die-to-die variations. Second, we move to another peer-technology which is 28nm FD-SOI as a comparative study, keeping the SRAM cell as the test block, more advanced study is carried out considering the cell‘s stability and the evolution from dynamic to static metrics

Four-injector variability modeling of FinFET predictive technology models

The usual way of modeling variability using threshold voltage shift and drain current amplification is becoming inaccurate as new sources of variability appear in sub-22nm devices. In this work we apply the four-injector approach for variability modeling to the simulation of SRAMs with predictive technology models from 20nm down to 7nm nodes. We show that the SRAMs, designed following ITRS roadmap, present stability metrics higher by at least 20% compared to a classical variability modeling approach. Speed estimation is also pessimistic, whereas leakage is underestimated if sub-threshold slope and DIBL mismatch and their correlations with threshold voltage are not considered