Common Subexpression Elimination in a Lazy Functional Language

Common subexpression elimination is a well-known compiler optimisation that saves time by avoiding the repetition of the same computation. To our knowledge it has not yet been applied to lazy functional programming languages, although there are several advantages. First, the referential transparency of these languages makes the identification of common subexpressions very simple. Second, more common subexpressions can be recognised because they can be of arbitrary type whereas standard common subexpression elimination only shares primitive values. However, because lazy functional languages decouple program structure from data space allocation and control flow, analysing its effects and deciding under which conditions the elimination of a common subexpression is beneficial proves to be quite difficult. We developed and implemented the transformation for the language Haskell by extending the Glasgow Haskell compiler and measured its effectiveness on real-world programs

Common Subexpression Elimination in Dotty

Common subexpression elimination is a well-known compiler optimisa- tion that improves running time of compiled applications by avoiding the repetition of the same computation. Although it has been implemented on a low level such as bytecode, it misses multiple opportunities that are available on high level, such as optimizing lazy vals. We developed and implemented the transformation for Scala in a new mini-phase in the Dotty Compiler

Common Subexpressions are Uncommon in Lazy Functional Languages

Common subexpression elimination is a well-known compiler optimisation that saves time by avoiding the repetition of the same computation. In lazy functional languages, referential transparency renders the identification of common subexpressions very simple. More common subexpressions can be recognised because they can be of arbitrary type whereas standard common subexpression elimination only shares primitive values. However, because lazy functional languages decouple program structure from data space allocation and control flow, analysing its effects and deciding under which conditions the elimination of a common subexpression is beneficial proves to be quite difficult. We developed and implemented the transformation for the language Haskell by extending the Glasgow Haskell compiler. On real-world programs the transformation showed nearly no effect. The reason is that common subexpressions whose elimination could speed up programs are uncommon in lazy functional languages

Mapping Applications to an FPFA Tile

This paper introduces a transformational design method which can be used to map code written in a high level source language, like C, to a coarse grain reconfigurable architecture. The source code is first translated into a control data flow graph (CDFG), which is minimized using a set of behaviour preserving transformations, such as dependency analysis, common subexpression elimination, etc. After applying graph clustering, scheduling and allocation transformations on this minimized graph, it can be mapped onto the target architecture

Certification of Compiler Optimizations using Kleene Algebra with Tests

We use Kleene algebra with tests to verify a wide assortment of common compiler optimizations, including dead code elimination, common subexpression elimination, copy propagation, loop hoisting, induction variable elimination, instruction scheduling, algebraic simplification, loop unrolling, elimination of redundant instructions, array bounds check elimination, and introduction of sentinels. In each of these cases, we give a formal equational proof of the correctness of the optimizing transformation

RECONFIGURABLE LOW POWER AND AREA EFFICIENT ESPFFIR FILTER USING VHBCSE MULTIPLIER

Reconfigurable Even Symmetric Parallel Fast Finite Impulse Response (RESPFFIR) filter shall be utilized as the Processing Element (PE) in Software Defined Radio (SDR) design to improve the throughput. The number of multipliers required in RESPFFIR filter increases when parallelism length increases. The Constant Multiplier (CM) technique is used to diminish the power consumption in FIR filters by reducing the number of Logical Operators (LO) and Logical Depth (LD). Binary Common Subexpression Elimination (BCSE) method is suitable to exploit symmetric coefficient in FIR filters. The Vertical Horizontal Binary Common Subexpression Elimination (VHBCSE) technique based Constant Multiplier (CM) design further diminish the number of LO and LD. The 2-bit BCSE algorithm has been applied vertically across neighboring coefficients and HCSE makes use of CSs that arise within each coefficient to eradicate redundant computations, which intern reduce logical operator in constant multiplier. This paper presents the design of Reconfigurable Even Symmetric Parallel Fast Finite Impulse Response (RESPFFIR) filter using VHBCSE based CM multiplier, which is reconfigurable with reduced power and area consumption without degrading the throughput. The power consumption reduces by 12% and the area required gets reduced by 24% in the proposed design when compared with existing CSE Hcub-n Multiple Constant Multiplier based  ESPFFIR filter design. The analysis is done using Cadence RC synthesize tools

GENETIC ALGORITHM CONTROLLED COMMON SUBEXPRESSION ELIMINATION FOR SPILL-FREE REGISTER ALLOCATION

As code complexity increases, maxlive increases. This is especially true in the case of the Kentucky If-Then-Else architecture proposed for Nanocontrollers. To achieve low circuit complexity, computations are decomposed to bit-level operations, thus generating large blocks of code with complex dependence structures. Additionally, the Nanocontroller architecture allows for only a small number of single bit registers and no extra memory. The assumption of an infinite number of registers made during code generation becomes a huge problem during register allocation because the small number of registers and no additional memory. The large basic blocks mean that maxlive almost always exceeds the number of registers and the traditional methods of register allocation such as instruction re-ordering and register spill/reload cannot be applied trivially. This thesis deals with finding a solution to reduce maxlive for successful register allocation using Genetic Algorithms