349 research outputs found

    Investigation of Efficient Unified Threat Management in Enterprise Security

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    This thesis explores the problems that exist today with perimeter security in data communications specifically the disparate architecture that exists to mitigate risk. Currently there are many different components to the enterprise security perimeter that are not cohesive and do not collaborate well to form an efficient, scalable, operationally supportable gateway design. The thesis breaks down this problem by illustrating the shortcomings of current technologies. These illustrations are used in conjunction with published research and authored research to provide solid footing for the idea of a unified threat management or UTM model. In this model, threat prevention techniques are consolidated into a single logical operating environment that leverages advances in next generation firewalls, intrusion prevention systems, content filtering and antivirus technologies. The results of this investigation are provided in a matrix that shows strengths and weaknesses with a consolidated unified model

    Architecting a One-to-many Traffic-Aware and Secure Millimeter-Wave Wireless Network-in-Package Interconnect for Multichip Systems

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    With the aggressive scaling of device geometries, the yield of complex Multi Core Single Chip(MCSC) systems with many cores will decrease due to the higher probability of manufacturing defects especially, in dies with a large area. Disintegration of large System-on-Chips(SoCs) into smaller chips called chiplets has shown to improve the yield and cost of complex systems. Therefore, platform-based computing modules such as embedded systems and micro-servers have already adopted Multi Core Multi Chip (MCMC) architectures overMCSC architectures. Due to the scaling of memory intensive parallel applications in such systems, data is more likely to be shared among various cores residing in different chips resulting in a significant increase in chip-to-chip traffic, especially one-to-many traffic. This one-to-many traffic is originated mainly to maintain cache-coherence between many cores residing in multiple chips. Besides, one-to-many traffics are also exploited by many parallel programming models, system-level synchronization mechanisms, and control signals. How-ever, state-of-the-art Network-on-Chip (NoC)-based wired interconnection architectures do not provide enough support as they handle such one-to-many traffic as multiple unicast trafficusing a multi-hop MCMC communication fabric. As a result, even a small portion of such one-to-many traffic can significantly reduce system performance as traditional NoC-basedinterconnect cannot mask the high latency and energy consumption caused by chip-to-chipwired I/Os. Moreover, with the increase in memory intensive applications and scaling of MCMC systems, traditional NoC-based wired interconnects fail to provide a scalable inter-connection solution required to support the increased cache-coherence and synchronization generated one-to-many traffic in future MCMC-based High-Performance Computing (HPC) nodes. Therefore, these computation and memory intensive MCMC systems need an energy-efficient, low latency, and scalable one-to-many (broadcast/multicast) traffic-aware interconnection infrastructure to ensure high-performance. Research in recent years has shown that Wireless Network-in-Package (WiNiP) architectures with CMOS compatible Millimeter-Wave (mm-wave) transceivers can provide a scalable, low latency, and energy-efficient interconnect solution for on and off-chip communication. In this dissertation, a one-to-many traffic-aware WiNiP interconnection architecture with a starvation-free hybrid Medium Access Control (MAC), an asymmetric topology, and a novel flow control has been proposed. The different components of the proposed architecture are individually one-to-many traffic-aware and as a system, they collaborate with each other to provide required support for one-to-many traffic communication in a MCMC environment. It has been shown that such interconnection architecture can reduce energy consumption and average packet latency by 46.96% and 47.08% respectively for MCMC systems. Despite providing performance enhancements, wireless channel, being an unguided medium, is vulnerable to various security attacks such as jamming induced Denial-of-Service (DoS), eavesdropping, and spoofing. Further, to minimize the time-to-market and design costs, modern SoCs often use Third Party IPs (3PIPs) from untrusted organizations. An adversary either at the foundry or at the 3PIP design house can introduce a malicious circuitry, to jeopardize an SoC. Such malicious circuitry is known as a Hardware Trojan (HT). An HTplanted in the WiNiP from a vulnerable design or manufacturing process can compromise a Wireless Interface (WI) to enable illegitimate transmission through the infected WI resulting in a potential DoS attack for other WIs in the MCMC system. Moreover, HTs can be used for various other malicious purposes, including battery exhaustion, functionality subversion, and information leakage. This information when leaked to a malicious external attackercan reveals important information regarding the application suites running on the system, thereby compromising the user profile. To address persistent jamming-based DoS attack in WiNiP, in this dissertation, a secure WiNiP interconnection architecture for MCMC systems has been proposed that re-uses the one-to-many traffic-aware MAC and existing Design for Testability (DFT) hardware along with Machine Learning (ML) approach. Furthermore, a novel Simulated Annealing (SA)-based routing obfuscation mechanism was also proposed toprotect against an HT-assisted novel traffic analysis attack. Simulation results show that,the ML classifiers can achieve an accuracy of 99.87% for DoS attack detection while SA-basedrouting obfuscation could reduce application detection accuracy to only 15% for HT-assistedtraffic analysis attack and hence, secure the WiNiP fabric from age-old and emerging attacks

    Modelling and Simulation of SIP and IAX Sessions

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    Import 03/11/2016My thesis is focused on simulating a functioning model of SIP and IAX and compare these two VoIP protocols. This is done by implementing an Asterisk server onto two virtual machines with Ubuntu operating system where I build a trunking system for each protocol, tested it by calling the peers in both directions, captured the traffic passing through and analysed it with Wireshark. The acquired data is then implemented and presented on a chart form for a better view and comparison of the two parallel protocols.Moje práce je zaměřena na simulaci funkčnosti modelu SIP a IAX a porovnání těchto dvou VoIP protokolů. To je provedeno zavedením Asteriskem serveru na dva virtuální počítaček s operačním systémem Ubuntu, kde je vybudován trunking systém pro každý protokol a to tak, že spojuje volající v obou směrech, zachycuje průchod, a analyzuje pomocí Wireshark. Získaná data jsou pak použita a prezentována ve formě grafů pro lepší přehlednost a srovnání obou paralelních protokolů.440 - Katedra telekomunikační technikydobř
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