A Framework for an Automated Compilation System for Reconfigurable Architectures

The advent of the Field Programmable Gate Array has allowed the implementation of runtime reconfigurable computer systems. These systems are capable of configuring their hardware to provide custom hardware support for software applications. Since these architectures can be reconfigured during operation, they are able to provide hardware support for a variety of applications, without removal from the system. The Air Force is currently investigating reconfigurable architectures for avionics and signal processing applications. This thesis investigates the problem of automating the application development process for reconfigurable architectures. The lack of automated development support is a major limiting factor in the use of these systems. This thesis creates a framework for a reconfigurable compiler, which automatically implements a single high level language specification as a reconfigurable hardware/software application. The major tasks in the process are examined, and possible methods for implementation are investigated. A prototype reconfigurable compiler has been developed to demonstrate the feasibility of important concepts, and to uncover additional areas of difficulty

Hierarchical Transactions for Hardware/Software Cosynthesis

Modern heterogeneous devices provide of a variety of computationally diverse components holding tremendous performance and power capability. Hardware-software cosynthesis offers system-level synthesis and optimization opportunities to realize the potential of these evolving architectures. Efficiently coordinating high-throughput data to make use of available computational resources requires a myriad of distributed local memories, caching structures, and data motion resources. In fact, storage, caching, and data transfer components comprise the majority of silicon real estate. Conventional automated approaches, unfortunately, do not effectively represent applications in a way that captures data motion and state management which dictate dominant system costs. Consequently, existing cosynthesis methods suffer from poor utility of computational resources. Automated cosynthesis tailored towards memory-centric optimizations can address the challenge, adapting partitioning, scheduling, mapping, and binding techniques to maximize overall system utility.This research presents a novel hierarchical transaction model that formalizes state and control management through an abstract data/control encapsulation semantic. It is designed from the ground-up to enable efficient synthesis across heterogeneous system components, with an emphasis on memory capacity constraints. It intrinsically encourages a high degree of concurrency and latency tolerance, and provides verification tools to ensure correctness. A unique data/execution hierarchical encapsulation framework guarantees scalable analysis, supporting a novel concept of state and control mobility. A front-end language allows concise expression of designer intent, and is structured with synthesis in mind. Designers express families of valid executions in a minimal format through high-level dependencies, type systems, and computational relationships, allowing synthesis tools to manage lower-level details. This dissertation introduces and exercises the model, discussing language construction, demonstrating control and data-dominated applications, and presenting a synthesis path that exhibits near-linear scalability with problem size

Digital processors performance estimation applied to low cost, three-phase electrical machines

Orientador: Ernesto Ruppert FilhoDissertação (mestrado) - Universidade Estadual de Campinas, Faculdade de Engenharia Eletrica e de ComputaçãoResumo: Este trabalho tem como objetivo apresentar um avaliador de desempenho de processadores digitais para utilização em aplicações de controle de motores de indução trifásicos, .especialmente aquelas destinadas a aplicações de baixo custo e adequadas a produtos de consumo. A concepção destes produtos exige que o processador seja corretamente dimensionado uma vez que o custo deste dispositivo é significativo face ao custo total do acionamento. .O método de avaliação aqui proposto utiliza um conjunto de métricas que permite predizer se um dado processador irá atender às restrições de tempo impostas pela aplicação, de forma a escalonar todas as tarefas que a compõe, bem como estimará o tamanho da memória de programa necessária para implementá-la. Os dados de diversos processadores disponíveis comercialmente foram aplicados no método de avaliação aqui proposto e um deles foi utilizado no desenvolvimento de um protótipo experimental, onde se coletaram dados para verificar a eficácia do avaliador. Estes resultados, bem como as divergências entre o real e o avaliado, estão apresentados neste trabalhoAbstract: The aim of this work is to show a digital processor performance simulator, to be used in three-phase induction motor control, specially those which are used in low cost products. The conception of these products demands the correct processor's specification, because its cost is expressive facing the overall drive's cost. The proposed simulation method uses a metrics set which enables to predict if one microprocessor will be in compliance with timing constraints imposed by the application in order to schedule all the software tasks, as well will estimate the necessary program memory size to implement it. Several commercially available microprocessor's data, were used with this simulation method and one of them were chose to be used in an experimental laboratory prototype, in order to collect data to verify the effectiveness of the proposed method. The results, as well the divergences between experimental and simulation, are shown in this workMestradoAutomaçãoMestre em Engenharia Elétric