High-rate self-synchronizing codes

Self-synchronization under the presence of additive noise can be achieved by allocating a certain number of bits of each codeword as markers for synchronization. Difference systems of sets are combinatorial designs which specify the positions of synchronization markers in codewords in such a way that the resulting error-tolerant self-synchronizing codes may be realized as cosets of linear codes. Ideally, difference systems of sets should sacrifice as few bits as possible for a given code length, alphabet size, and error-tolerance capability. However, it seems difficult to attain optimality with respect to known bounds when the noise level is relatively low. In fact, the majority of known optimal difference systems of sets are for exceptionally noisy channels, requiring a substantial amount of bits for synchronization. To address this problem, we present constructions for difference systems of sets that allow for higher information rates while sacrificing optimality to only a small extent. Our constructions utilize optimal difference systems of sets as ingredients and, when applied carefully, generate asymptotically optimal ones with higher information rates. We also give direct constructions for optimal difference systems of sets with high information rates and error-tolerance that generate binary and ternary self-synchronizing codes.Comment: 9 pages, no figure, 2 tables. Final accepted version for publication in the IEEE Transactions on Information Theory. Material presented in part at the International Symposium on Information Theory and its Applications, Honolulu, HI USA, October 201

Synchronization for capacity -approaching coded communication systems

The dissertation concentrates on synchronization of capacity approaching error-correction codes that are deployed in noisy channels with very low signal-to-noise ratio (SNR). The major topics are symbol timing synchronization and frame synchronization.;Capacity-approaching error-correction codes, like turbo codes and low-density parity-check (LDPC) codes, are capable of reaching very low bit error rates and frame error rates in noisy channels by iterative decoding. To fully achieve the potential decoding capability of Turbo codes and LDPC codes, proper symbol timing synchronization, frame synchronization and channel state estimation are required. The dissertation proposes a joint estimator of symbol time delay and channel SNR for symbol timing recovery, and a maximum a posteriori (MAP) frame synchronizer for frame synchronization.;Symbol timing recovery is implemented by sampling and interpolation. The received signal is sampled multiple times per symbol period with unknown delay and unknown SNR. A joint estimator estimates the time delay and the SNR. The signal is rebuilt by interpolating available samples using estimated time delay. The intermediate decoding results enable decision-feedback estimation. The estimates of time delay and SNR are refined by iterative processing. This refinement improves the system performance significantly.;Usually the sampling rate is assumed to be a strict integer multiple of the symbol rate. However, in a practical system the local oscillators in the transmitter and the receiver may have random drifts. Therefore the sampling rate is no longer an exact multiple of the symbol rate, and the sampling time follows a random walk. This random walk may harm the system performance severely. The dissertation analyzes the effect of random time walks and proposes to mitigate the effect by overlapped sliding windows and iterative processing.;Frame synchronization is required to find the correct boundaries of codewords. MAP frame synchronization in the sense of minimizing the frame sync failure rate is investigated. The MAP frame synchronizer explores low-density parity-check attributes of the capacity-approaching codes. The accuracy of frame synchronization is adequate for considered coded systems to work reliably under very low SNR

Error resilient image transmission using T-codes and edge-embedding

Current image communication applications involve image transmission over noisy channels, where the image gets damaged. The loss of synchronization at the decoder due to these errors increases the damage in the reconstructed image. Our main goal in this research is to develop an algorithm that has the capability to detect errors, achieve synchronization and conceal errors.;In this thesis we studied the performance of T-codes in comparison with Huffman codes. We develop an algorithm for the selection of best T-code set. We have shown that T-codes exhibit better synchronization properties when compared to Huffman Codes. In this work we developed an algorithm that extracts edge patterns from each 8x8 block, classifies edge patterns into different classes. In this research we also propose a novel scrambling algorithm to hide edge pattern of a block into neighboring 8x8 blocks of the image. This scrambled hidden data is used in the detection of errors and concealment of errors. We also develop an algorithm to protect the hidden data from getting damaged in the course of transmission

Classification of the Deletion Correcting Capabilities of Reed–Solomon Codes of Dimension Over Prime Fields

Deletion correction codes have been used for transmission synchronization and, more recently, tracing pirated media. A generalized Reed-Solomon (GRS) code, denoted by GRSk(l,q,alpha,v), is a code of length l over GF(q) with qk codewords. These codes have an efficient decoding algorithm and have been widely used for error correction and detection. It was recently demonstrated that GRS codes are also capable of correcting deletions. We consider a subclass of GRS codes with dimension k=2 and q prime, and study them with respect to deletion correcting capability. We give transformations that either preserve the code or maintain its deletion correction capability. We use this to define equivalent codes; and then use exhaustive and selective computer searches to find inequivalent codes with the highest deletion correcting capabilities. We show that, for the class under consideration, up to l-3 deletions may be corrected. We also show that for lles36 there exist codes with q2 codewords such that receiving only 3 out of t transmitted symbols of a codeword is enough to recover the codeword, thus meeting the bound specified above. We also specify some nice codes which are associated with the smallest field possible for codes of a given length and deletion correcting capability. Some of the identified codes are unique, with respect to the defined equivalence

Benchmarking the Intel®Xeon®Platinum 8160 Processor

This report presents a set of results for different microbenchmarks and applications on the Intel Xeon Platinum8160 Processor, formerly known as Skylake. For simplicity, we will use both Skylake and SKX to refer to this processor. We use the Skylake nodes that will be available in Stampede2. This systemwill provide Intel Knights Landing and Skylake chips interconnected by a 100 Gb/sec Intel Omni-Path (OPA) network with a fat tree topology. The peak performance of the system will be 18 PF.Texas Advanced Computing Center (TACC