Learning and Communications Co-Design for Remote Inference Systems: Feature Length Selection and Transmission Scheduling

In this paper, we consider a remote inference system, where a neural network is used to infer a time-varying target (e.g., robot movement), based on features (e.g., video clips) that are progressively received from a sensing node (e.g., a camera). Each feature is a temporal sequence of sensory data. The learning performance of the system is determined by (i) the timeliness and (ii) the temporal sequence length of the features, where we use Age of Information (AoI) as a metric for timeliness. While a longer feature can typically provide better learning performance, it often requires more channel resources for sending the feature. To minimize the time-averaged inference error, we study a learning and communication co-design problem that jointly optimizes feature length selection and transmission scheduling. When there is a single sensor-predictor pair and a single channel, we develop low-complexity optimal co-designs for both the cases of time-invariant and time-variant feature length. When there are multiple sensor-predictor pairs and multiple channels, the co-design problem becomes a restless multi-arm multi-action bandit problem that is PSPACE-hard. For this setting, we design a low-complexity algorithm to solve the problem. Trace-driven evaluations suggest that the proposed co-designs can significantly reduce the time-averaged inference error of remote inference systems.Comment: 41 pages, 8 figures. The manuscript has been submitted to IEEE Journal on Selected Areas in Information Theor

Raising the abstraction level of hardware software co-designs

As lithographic processes’ size to manufacture transistors shrink, the number of available transistors on integrated circuits (IC) increases. Newly manufactured ICs require innovations to leverage improved performances or area occupation, and feature more and more components on the same chip, which work together and/or independently to provide an advanced set of functions. The complexity of hardware design flows consequently increased: from circuit description to functional verification and in-system interface, every stage is now more and more driven by a cross-product function between a set of reusable functional units and constraints to target a specific technology (ASIC, FPGAs etc…) and configuration. This diversity in the possible outputs for a set of components calls for the development of new methodologies to raise the abstraction level in the design flows. A better abstraction allows optimizing and automating more processes, from component specification to final implementation and interfacing. New Abstraction levels have always emerged through industry standards like Verilog and VHDL for digital circuit description, SystemVerilog/UVM/e for functional verification, or by vendor specific toolchains. However, standards and software toolchains usually lack flexibility as they operate for a bounded range of functionalities. This thesis presents some novel applications covering various stages of the design flow, ranging from digital design input (register file generator) and ASIC circuit implementation (Hierarchical Floorplaning), up to in-system IC integration (Part design language). They are backed by a generic software design methodology based on functional programming used to develop domain specific languages embedded in the TCL interpreter. To complete the design flow path from circuit implementation to software integration, a hardware-software interfacing point linked with the Register File Generator design tool will be presented. It is based on a generic and innovative XML-Data binding technology which was developed during this work. The iterative loop between application definition and flexible software components reuse presented along this work also provides a general guideline to develop future design flow components, and guarantee their integration in any target environment

Simulation Environment with Customized RISC-V Instructions for Logic-in-Memory Architectures

Nowadays, various memory-hungry applications like machine learning algorithms are knocking "the memory wall". Toward this, emerging memories featuring computational capacity are foreseen as a promising solution that performs data process inside the memory itself, so-called computation-in-memory, while eliminating the need for costly data movement. Recent research shows that utilizing the custom extension of RISC-V instruction set architecture to support computation-in-memory operations is effective. To evaluate the applicability of such methods further, this work enhances the standard GNU binary utilities to generate RISC-V executables with Logic-in-Memory (LiM) operations and develop a new gem5 simulation environment, which simulates the entire system (CPU, peripherals, etc.) in a cycle-accurate manner together with a user-defined LiM module integrated into the system. This work provides a modular testbed for the research community to evaluate potential LiM solutions and co-designs between hardware and software

SystemC Through the Looking Glass : Non-Intrusive Analysis of Electronic System Level Designs in SystemC

Due to the ever increasing complexity of hardware and hardware/software co-designs, developers strive for higher levels of abstractions in the early stages of the design flow. To address these demands, design at the Electronic System Level (ESL) has been introduced. SystemC currently is the de-facto standard for ESL design. The extraction of data from system designs written in SystemC is thereby crucial e.g. for the proper understanding of a given system. However, no satisfactory support of reflection/introspection of SystemC has been provided yet. Previously proposed methods for this purpose %introduced to achieve the goal nonetheless either focus on static aspects only, restrict the language means of SystemC, or rely on modifications of the compiler and/or parser. In this thesis, approaches that overcome these limitations are introduced, allowing the extraction of information from a given SystemC design without changing the SystemC library or the compiler. The proposed approaches retrieve both, static and dynamic (i.e. run-time) information