Saw-Less radio receivers in CMOS

Smartphones play an essential role in our daily life. Connected to the internet, we can easily keep in touch with family and friends, even if far away, while ever more apps serve us in numerous ways. To support all of this, higher data rates are needed for ever more wireless users, leading to a very crowded radio frequency spectrum. To achieve high spectrum efficiency while reducing unwanted interference, high-quality band-pass filters are needed. Piezo-electrical Surface Acoustic Wave (SAW) filters are conventionally used for this purpose, but such filters need a dedicated design for each new band, are relatively bulky and also costly compared to integrated circuit chips. Instead, we would like to integrate the filters as part of the entire wireless transceiver with digital smartphone hardware on CMOS chips. The research described in this thesis targets this goal. It has recently been shown that N-path filters based on passive switched-RC circuits can realize high-quality band-select filters on CMOS chips, where the center frequency of the filter is widely tunable by the switching-frequency. As CMOS downscaling following Moore’s law brings us lower clock-switching power, lower switch on-resistance and more compact metal-to-metal capacitors, N-path filters look promising. This thesis targets SAW-less wireless receiver design, exploiting N-path filters. As SAW-filters are extremely linear and selective, it is very challenging to approximate this performance with CMOS N-path filters. The research in this thesis proposes and explores several techniques for extending the linearity and enhancing the selectivity of N-path switched-RC filters and mixers, and explores their application in CMOS receiver chip designs. First the state-of-the-art in N-path filters and mixer-first receivers is reviewed. The requirements on the main receiver path are examined in case SAW-filters are removed or replaced by wideband circulators. The feasibility of a SAW-less Frequency Division Duplex (FDD) radio receiver is explored, targeting extreme linearity and compression Irequirements. A bottom-plate mixing technique with switch sharing is proposed. It improves linearity by keeping both the gate-source and gate-drain voltage swing of the MOSFET-switches rather constant, while halving the switch resistance to reduce voltage swings. A new N-path switch-RC filter stage with floating capacitors and bottom-plate mixer-switches is proposed to achieve very high linearity and a second-order voltage-domain RF-bandpass filter around the LO frequency. Extra out-of-band (OOB) rejection is implemented combined with V-I conversion and zero-IF frequency down-conversion in a second cross-coupled switch-RC N-path stage. It offers a low-ohmic high-linearity current path for out-of-band interferers. A prototype chip fabricated in a 28 nm CMOS technology achieves an in-band IIP3 of +10 dBm , IIP2 of +42 dBm, out-of-band IIP3 of +44 dBm, IIP2 of +90 dBm and blocker 1-dB gain-compression point of +13 dBm for a blocker frequency offset of 80 MHz. At this offset frequency, the measured desensitization is only 0.6 dB for a 0-dBm blocker, and 3.5 dB for a 10-dBm blocker at 0.7 GHz operating frequency (i.e. 6 and 9 dB blocker noise figure). The chip consumes 38-96 mW for operating frequencies of 0.1-2 GHz and occupies an active area of 0.49 mm2. Next, targeting to cover all frequency bands up to 6 GHz and achieving a noise figure lower than 3 dB, a mixer-first receiver with enhanced selectivity and high dynamic range is proposed. Capacitive negative feedback across the baseband amplifier serves as a blocker bypassing path, while an extra capacitive positive feedback path offers further blocker rejection. This combination of feedback paths synthesizes a complex pole pair at the input of the baseband amplifier, which is up-converted to the RF port to obtain steeper RF-bandpass filter roll-off than the conventional up-converted real pole and reduced distortion. This thesis explains the circuit principle and analyzes receiver performance. A prototype chip fabricated in 45 nm Partially Depleted Silicon on Insulator (PDSOI) technology achieves high linearity (in-band IIP3 of +3 dBm, IIP2 of +56 dBm, out-of-band IIP3 = +39 dBm, IIP2 = +88 dB) combined with sub-3 dB noise figure. Desensitization due to a 0-dBm blocker is only 2.2 dB at 1.4 GHz operating frequency. IIFinally, to demonstrate the performance of the implemented blocker-tolerant receiver chip designs, a test setup with a real mobile phone is built to verify the sensitivity of the receiver chip for different practical blocking scenarios

Highly Linear Filtering TIA for 5G wireless standard and beyond

The demand for high data rates in emerging wireless standards is a result of the growing number of wireless device subscribers. This demand is met by increasing the channel bandwidth in accordance with historical trends. As MIMO technology advances, more bands and antennas are expected to be used. The most recent 5G standard makes use of mm-wave bands above 24GHz to expand the channel bandwidth. Channel bandwidth can exceed 2GHz when carrier aggregation is used. From the receiver’s point of view, this makes the baseband filter’s design, which is often a TIA, more difficult. This is due to the fact that as the bandwidth approaches the GHz range, the TIA’s UGBW should be more than 5GHz and it should have a high loop gain up to high frequencies. A closed-loop TIA with configurable bandwidth up to 1.5GHz is described in this scenario. Operational Transconductance Amplifier (OTA) closed in shunt-feedback is the foundation of the TIA. The proposed OTA is based on FeedForward topology (FF) together with inductive peaking technique to ensure stability rather than using the traditional Miller compensation technique. The TIA is able to produce GLoop unity gain bandwidth of 7.5GHz and high loop gain (i.e. 27dB @ 1GHz) using this method. The mixer and LNA’s linearity will benefit from this. Utilizing TSMC 28nm CMOS technology, a prototype has been created using this methodology. The output integrated noise from 20MHz to 1.5GHz is lower than 300μVrms with a power consumption of 17mW, and the TIA achieves In-band OIP3 of 33dBm. Additionally, a direct-conversion receiver for 5G applications is described. The 7GHz RF signal is down-converted to baseband by the receiver. Two cascaded LNTAs based on a common-gate transformer-based design make up the frontend. With an RF gain of 80mS and a gain variability of 31dB, it provides wideband matching from 6GHz to 8GHz. A double-balanced passive mixer is driven by the LNTA. The channel bandwidth from 50MHz to 2GHz is covered by two baseband paths. The first path, called as the low frequency path (LF), covers the channel bandwidth ranging from 50MHz to 400 MHz. In contrast, the second path, called as the high frequency path (HF), covers the channel bandwidth between 800MHz and 2GHz. Two baseband provide gain variability of 14dB, making the overall receiver able to have a gain configurability from 45dB to 0dB. Out-of-band (OOB) selectivity at 4 times the band-edge is greater than 33dB for each configurability. When the gain is at its maximum, the noise figure is less than 5.8dB, and the slope of the noise rise as the gain falls is less than 0.7dB/dB. The receiver guarantee an IB-OIP3 larger than 21dBm for any gain configuration. The receiver has been implemented in TSMC 28nm CMOS technology, consuming 51mW for LF path and 68mW for HF path. The measurement results are in perfect accordance with the requirements of the design

Design of PVT Tolerant Inverter Based Circuits for Low Supply Voltages

University of Minnesota Ph.D. dissertation. June 2015. Major: Electrical Engineering. Advisor: Ramesh Harjani. 1 computer file (PDF); xiv, 187 pages.Rapid advances in the field of integrated circuit design has been advantageous from the point of view of cost and miniaturization. Although technology scaling is advantageous to digital circuits in terms of increased speed and lower power, analog circuits strongly suffer from this trend. This is becoming a crucial bottle neck in the realization of a system on chip in scaled technology merging high-density digital parts, with high performance analog interfaces. This is because scaled technologies reduce the output impedance (gain) and supply voltage which limits the dynamic range (output swing). One way to mitigate the power supply restrictions is to move to current mode circuit circuit design rather than voltage mode designs. This thesis focuses on designing Process Voltage and Temperature (PVT) tolerant base band circuits at lower supply voltages and in lower technologies. Inverter amplifiers are known to have better transconductance efficiency, better noise and linearity performance. But inverters are prone to PVT variations and has poor CMRR and PSRR. To circumvent the problem, we have proposed various biasing schemes for inverter like semi constant current biasing, constant current biasing and constant gm biasing. Each biasing technique has its own advantages, like semi constant current biasing allows to select different PMOS and NMOS current. This feature allows for higher inherent inverter linearity. Similarly constant current and constant gm biasing allows for reduced PVT sensitivity. The inverter based OTA achieves a measured THD of -90.6 dB, SNR of 78.7 dB, CMRR 97dB, PSRR 61 dB wile operating from a nominal power of 0.9V and at output swing of 0.9V{pp,diff} in TSMC 40nm general purpose process. Further the measured third harmonic distortion varies approximately by 11.5dB with 120C variation in temperature and 9dB with a 18% variation in supply voltage. The linearity can be increased by increasing the loop gain and bandwidth in a negative feedback circuit or by increasing the over drive voltage in open loop architectures. However both these techniques increases the noise contribution of the circuit. There exist a trade off between noise and linearity in analog circuits. To circumvent this problem, we have introduced nonlinear cancellation techniques and noise filtering techniques. An analog-to-digital converter (ADC) driver which is capable of amplifying the continuous time signal with a gain of 8 and sample onto the input capacitor(1pF) of 1 10 bit successive approximation register (SAR) ADC is designed in TSMC 65nm general purpose process. This exploits the non linearity cancellation in current mirror and also allows for higher bandwidth operation by decoupling closed loop gain from the negative feedback loop. The noise from the out of band is filtered before sampling leading to low noise operation. The measured design operates at 100MS/s and has an OIP_3 of 40dBm at the nyquist rate, noise power spectral density of 17nV/sqrt{Hz} and inter modulation distortion of 65dB. The intermodulation distortion variation across 10 chips is 6dB and 4dB across a temperature variation of 120C. Non linearity cancellation is exploited in designing two filters, an anti alias filter and a continuously tunable channel select filter. Traditional active RC filters are based on cascade of integrators. These create multiple low impedance nodes in the circuit which results in a higher noise. We propose a real low pass filter based filter architecture rather than traditional integrator based approach. Further the entire filtering operation takes place in current domain to circumvent the power supply limitations. This also facilitates the use of tunable non linear metal oxide semiconductor capacitor (MOSCAP) as filter capacitors. We introduce techniques of self compensation to use the filter resistor and capacitor as compensation capacitor for lower power. The anti alias filter designed for 50MHz bandwidth is fabricated in IBM 65nm process achieves an IIP3 of 33dBm, while consuming 1.56mW from 1.2 V supply. The channel select filter is tunable from 34MHz to 314MHz and is fabricated in TSMC 65nm general purpose process. This filter achieves an OIP3 of 25.24 dBm at the maximum frequency while drawing 4.2mA from 1.1V supply. The measured intermodulation distortion varies by 5dB across 120C variation in temperature and 6.5dB across a 200mV variation in power supply. Further this filter presents a high impedance node at the input and a low impedance node at the output easing system integration. SAR ADCs are becoming popular at lower technologies as they are based on device switching rather than amplifying circuits. But recent SAR ADCs that have good energy efficiency have had relatively large input capacitance increasing the driver power. We present a 2X time interleaved (TI) SAR ADC which has the lowest input capacitance of 133fF in literature. The sampling capacitor is separated from the capacitive digital to analog converter (DAC) array by performing the input and DAC reference subtraction in the current domain rather than as done traditionally in charge domain. The proposed ADC is fabricated in TSMC's 65nm general purpose process and occupies an area of 0.0338 mm^2. The measured ADC spurious free dynamic range (SFDR) is 57dB and the measured effective number of bits (ENOB) at nyquist rate is 7.55 bit while using 1.55mW power from 1 V supply. A sub 1V reference circuit is proposed, that exploits the complementary to absolute temperature (CTAT) and proportional to absolute temperature (PTAT) voltages in the beta multiplier circuit to attain a stable voltage with temperature and power supply. A one-time calibration is integrated in the architecture to get a good performance over process. Chopper stabilization is employed to reduce the flicker noise of the reference circuit. The prototype was simulated in TSMC 65nm process and we obtain the nominal output of 236mW, while consuming 0.7mW from power supply. Simulations show a temperature coefficient of 18 ppmC from -40 to 100C and with a power supply ranging from 0.8 to 2V

Low-Power Wireless Medical Systems and Circuits for Invasive and Non-Invasive Applications

Approximately 75% of the health care yearly budget of public health systems around the world is spent on the treatment of patients with chronic diseases. This, along with advances on the medical and technological fields has given rise to the use of preventive medicine, resulting on a high demand of wireless medical systems (WMS) for patient monitoring and drug safety research. In this dissertation, the main design challenges and solutions for designing a WMS are addressed from system-level, using off-the-shell components, to circuit implementation. Two low-power oriented WMS aiming to monitor blood pressure of small laboratory animals (implantable) and cardiac-activity (12-lead electrocardiogram) of patients with chronic diseases (wearable) are presented. A power consumption vs. lifetime analysis to estimate the monitoring unit lifetime for each application is included. For the invasive/non-invasive WMS, in-vitro test benches are used to verify their functionality showing successful communication up to 2.1 m/35 m with the monitoring unit consuming 0.572 mA/33 mA from a 3 V/4.5 V power supply, allowing a two-year/ 88-hour lifetime in periodic/continuous operation. This results in an improvement of more than 50% compared with the lifetime commercial products. Additionally, this dissertation proposes transistor-level implementations of an ultra-low-noise/low-power biopotential amplifier and the baseband section of a wireless receiver, consisting of a channel selection filter (CSF) and a variable gain amplifier (VGA). The proposed biopotential amplifier is intended for electrocardiogram (ECG)/ electroencephalogram (EEG)/ electromyogram (EMG) monitoring applications and its architecture was designed focused on improving its noise/power efficiency. It was implemented using the ON-SEMI 0.5 µm standard process with an effective area of 360 µm2. Experimental results show a pass-band gain of 40.2 dB (240 mHz - 170 Hz), input referred noise of 0.47 Vrms, minimum CMRR of 84.3 dBm, NEF of 1.88 and a power dissipation of 3.5 µW. The CSF was implemented using an active-RC 4th order inverse-chebyshev topology. The VGA provides 30 gain steps and includes a DC-cancellation loop to avoid saturation on the sub-sequent analog-to-digital converter block. Measurement results show a power consumption of 18.75 mW, IIP3 of 27.1 dBm, channel rejection better than 50 dB, gain variation of 0-60dB, cut-off frequency tuning of 1.1-2.29 MHz and noise figure of 33.25 dB. The circuit was implemented in the standard IBM 0.18 µm CMOS process with a total area of 1.45 x 1.4 mm^(2). The presented WMS can integrate the proposed biopotential amplifier and baseband section with small modifications depending on the target signal while using the low-power-oriented algorithm to obtain further power optimization

Multi-band OFDM UWB receiver with narrowband interference suppression

A multi band orthogonal frequency division multiplexing (MB-OFDM) compatible ultra wideband (UWB) receiver with narrowband interference (NBI) suppression capability is presented. The average transmit power of UWB system is limited to -41.3 dBm/MHz in order to not interfere existing narrowband systems. Moreover, it must operate even in the presence of unintentional radiation of FCC Class-B compatible devices. If this unintentional radiation resides in the UWB band, it can jam the communication. Since removing the interference in digital domain requires higher dynamic range of analog front-end than removing it in analog domain, a programmable analog notch filter is used to relax the receiver requirements in the presence of NBI. The baseband filter is placed before the variable gain amplifier (VGA) in order to reduce the signal swing at the VGA input. The frequency hopping period of MB-OFDM puts a lower limit on the settling time of the filter, which is inverse proportional to notch bandwidth. However, notch bandwidth should be low enough not to attenuate the adjacent OFDM tones. Since these requirements are contradictory, optimization is needed to maximize overall performance. Two different NBI suppression schemes are tested. In the first scheme, the notch filter is operating for all sub-bands. In the second scheme, the notch filter is turned on during the sub-band affected by NBI. Simulation results indicate that the UWB system with the first and the second suppression schemes can handle up to 6 dB and 14 dB more NBI power, respectively. The results of this work are not limited to MB-OFDM UWB system, and can be applied to other frequency hopping systems

Frequency Translation loops for RF filtering-Theory and Design

Modern wireless transceivers are required to operate over a wide range of frequencies in order to support the multitude of currently available wireless standards. Wideband operation also enables future systems that aim for better utilization of the available spectrum through dynamic allocation. As such, co-existence problems like harmonic mixing and phase noise become a main concern. In particular, dealing with interfer- ence scenarios is crucial since they directly translate to higher linearity requirements in a receiver. With CMOS driving the consumer electronics market due to low cost and high level of integration demands, the continued increase in speed, mainly intended for digital applications, oers new possibilities for RF design to improve the linearity of front-end receivers. Furthermore, the readily available switches in CMOS have proven to be a viable alternative to traditional active mixers for frequency translation due to their high linearity, low flicker noise, and, most recently recognized, their impedance transformation properties. In this thesis, frequency translation feedback loops employing passive mixers are explored as a means to relax the linearity requirements in a front-end receiver by providing channel selectivity as early as possible in the receiver chain. The proposed receiver architecture employing such loop addresses some of the most common prob- lems of integrated RF lters, while maintaining their inherent tunability. Through a simplied and intuitive analysis, the operation of the receiver is first examined and the design parameters aecting the lter characteristics, such as band- width and stop-band rejection, are determined. A systematic procedure for analyzing the linearity of the receiver reveals the possibility of LNA distortion canceling, which decouples the trade-o between noise, linearity and harmonic radiation. Next, a detailed analysis of frequency translation loops using passive mixers is developed. Only highly simplied analysis of such loops is commonly available in literature. The analysis is based on an iterative procedure to address the complexity introduced by the presence of LO harmonics in the loop and the lack of reverse isolation in the mixers, and results in highly accurate expressions for the harmonic and noise transfer functions of the system. Compared to the alternative of applying general LPTV theory, the procedure developed oers more intuition into the operation of the system and only requires the knowledge of basic Fourier analysis. The solution is shown to be capable of predicting trade-os arising due to harmonic mixing and loop stability requirements, and is therefore useful for both system design and optimization. Finally, as a proof of concept, a chip prototype is designed in a standard 65nm CMOS process. The design occupies +12dBm. As such, the work presented in this thesis aims to provide a highly-integrated means for programmable RF channel selection in wideband receivers. The topic oers several possibilities for further research, either in terms of extending the viability of the system, for example by providing higher order ltering, or by improving performance, such as noise

High Performance Integrated Circuit Blocks for High-IF Wideband Receivers

Due to the demand for high‐performance radio frequency (RF) integrated circuit design in the past years, a system‐on‐chip (SoC) that enables integration of analog and digital parts on the same die has become the trend of the microelectronics industry. As a result, a major requirement of the next generation of wireless devices is to support multiple standards in the same chip‐set. This would enable a single device to support multiple peripheral applications and services. Based on the aforementioned, the traditional superheterodyne front‐end architecture is not suitable for such applications as it would require a complete receiver for each standard to be supported. A more attractive alternative is the highintermediate frequency (IF) radio architecture. In this case the signal is digitalized at an intermediate frequency such as 200MHz. As a consequence, the baseband operations, such as down‐conversion and channel filtering, become more power and area efficient in the digital domain. Such architecture releases the specifications for most of the front‐end building blocks, but the linearity and dynamic range of the ADC become the bottlenecks in this system. The requirements of large bandwidth, high frequency and enough resolution make such ADC very difficult to realize. Many ADC architectures were analyzed and Continuous‐Time Bandpass Sigma‐Delta (CT‐BP‐ΣΔ) architecture was found to be the most suitable solution in the high‐IF receiver architecture since they combine oversampling and noise shaping to get fairly high resolution in a limited bandwidth. A major issue in continuous‐time networks is the lack of accuracy due to powervoltage‐ temperature (PVT) tolerances that lead to over 20% pole variations compared to their discrete‐time counterparts. An optimally tuned BP ΣΔ ADC requires correcting for center frequency deviations, excess loop delay, and DAC coefficients. Due to these undesirable effects, a calibration algorithm is necessary to compensate for these variations in order to achieve high SNR requirements as technology shrinks. In this work, a novel linearization technique for a Wideband Low‐Noise Amplifier (LNA) targeted for a frequency range of 3‐7GHz is presented. Post‐layout simulations show NF of 6.3dB, peak S21 of 6.1dB, and peak IIP3 of 21.3dBm, respectively. The power consumption of the LNA is 5.8mA from 2V. Secondly, the design of a CMOS 6th order CT BP‐ΣΔ modulator running at 800 MHz for High‐IF conversion of 10MHz bandwidth signals at 200 MHz is presented. A novel transconductance amplifier has been developed to achieve high linearity and high dynamic range at high frequencies. A 2‐bit quantizer with offset cancellation is alsopresented. The sixth‐order modulator is implemented using 0.18 um TSMC standard analog CMOS technology. Post‐layout simulations in cadence demonstrate that the modulator achieves a SNDR of 78 dB (~13 bit) performance over a 14MHz bandwidth. The modulator’s static power consumption is 107mW from a supply power of ± 0.9V. Finally, a calibration technique for the optimization of the Noise Transfer Function CT BP ΣΔ modulators is presented. The proposed technique employs two test tones applied at the input of the quantizer to evaluate the noise transfer function of the ADC, using the capabilities of the Digital Signal Processing (DSP) platform usually available in mixed‐mode systems. Once the ADC output bit stream is captured, necessary information to generate the control signals to tune the ADC parameters for best Signal‐to‐Quantization Noise Ratio (SQNR) performance is extracted via Least‐ Mean Squared (LMS) software‐based algorithm. Since the two tones are located outside the band of interest, the proposed global calibration approach can be used online with no significant effect on the in‐band content

Voltage and Time-Domain Analog Circuit Techniques for Scaled CMOS Technologies

CMOS technology scaling has resulted in reduced supply voltage and intrinsic voltage gain of the transistor. This presents challenges to the analog circuit designers due to lower signal swing and achievable signal to noise ratio (SNR), leading to increased power consumption. At the same time, device speed has increased in lower design nodes, which has not been directly beneficial for analog circuit design. This thesis presents voltage-domain and time-domain circuit scaling friendly circuit architectures that minimize the power consumption and benefit from the increasing transistor speeds. In the voltage-domain, an on-the-fly gain selection block is demonstrated as an alternative to the traditional MDAC architecture to enhance the input dynamic range of a medium-resolution medium-speed analog-to-digital converter (ADC) at reduced supply voltages. The proposed design also eliminates the need for a reference buffer, thus providing power savings. The measured prototype enhances the input dynamic range of a 12bit, 40MSPS ADC to 80.6dB at 1.2V supply voltage. In the time-domain, a generic circuit design approach is presented, followed by an in-depth analysis of Voltage-Controlled-Oscillator based Operational Transconductance Amplifiers (VCO-OTAs). A discrete-time-domain small-signal model based on the zero crossings of the internal VCOs is developed to predict the stability, the step response, and the frequency response of the circuit when placed in feedback. The model accurately predicts the circuit behavior for an arbitrary input frequency, even as the VCO free-running frequency approaches the unity-gain bandwidth of the closed-loop system, where other intuitive small-signal models available in the literature fail. Next, we present an application of VCO-OTA in designing a baseband trans-impedance amplifier (TIA) for current-mode receivers as a scaling-friendly and power-efficient alternative to the inverter-based OTA. We illustrate a design methodology for the choice of the VCO-OTA parameters in the context of a receiver design with an example of a 20MHz RF-channel-bandwidth receiver operating at 2GHz. Receiver simulation results demonstrate an improvement of up to 12dB in blocker 1dB compression point (B1dB) for slightly higher power consumption or up to 2.6x power reduction of the TIA resulting in up to 2x power reduction of the receiver for similar B1dB performance. Next, we present some examples of VCO-OTAs. We first illustrate the benefit of a VCO-OTA in a low-dropout-voltage regulator to achieve a dropout voltage of only100mV and operating down to 0.8V input supply, compared to the prototype based on traditional OTA with a minimum dropout voltage of 150mV, operating at a minimum of 1.2V supply. Both the capacitor-less prototypes can drive up to 1nF load capacitor and provide a current of 60mA. The next prototype showcases a method to reduce the power consumption of a VCO-OTA and spurs at the VCO frequency, with an application in the design of a fourth-order Butterworth filter at 4MHz. The thesis concludes with a design example of 0.2V VCO-OTA

Analysis and Design of Wideband Low Noise Amplifier with Digital Control

The design issues in designing low noise amplifier (LNA) for Software-Defined-Radio (SDR) are reviewed. An inductor-less wideband low noise amplifier aiming at low frequency band (0.2-2GHz) for Software-Defined-Radio is presented. Shunt-shunt LNA with active feedback is used as the first stage which is carefully optimized for low noise and wide band applications. A digitally controlled second stage is employed to provide an additional 12dB gain control. A novel method is proposed to bypass the first stage without degrading input matching. This LNA is fabricated in a standard 0.18 um CMOS technology. The measurement result shows the proposed LNA has a gain range of 6dB-18dB at high gain mode and -12dB-0dB at low gain mode, as well as a –3dB bandwidth of 2GHz. The noise figure (NF) is 3.5-4.5dB in the high gain setting mode. It consumes 20mW from a 1.8V supply