Delay Extraction Based Equivalent Elmore Model For RLC On-Chip Interconnects

As feature sizes for VLSI technology is shrinking, associated with higher operating frequency, signal integrity analysis of on-chip interconnects has become a real challenge for circuit designers. For this purpose, computer-aided-design (CAD) tools are necessary to simulate signal propagation of on-chip interconnects which has been an active area for research. Although SPICE models exist which can accurately predict signal degradation of interconnects, they are computationally expensive. As a result, more effective and analytic models for interconnects are required to capture the response at the output of high speed VLSI circuits. This thesis contributes to the development of efficient and closed form solution models for signal integrity analysis of on-chip interconnects. The proposed model uses a delay extraction algorithm to improve the accuracy of two-pole Elmore based models used in the analysis of on-chip distributed RLC interconnects. In the proposed scheme, the time of fight signal delay is extracted without increasing the number of poles or affecting the stability of the transfer function. This algorithm is used for both unit step and ramp inputs. From the delay rational approximation of the transfer function, analytic fitted expressions are obtained for the 50% delay and rise time for unit step input. The proposed algorithm is tested on point to point interconnections and tree structure networks. Numerical examples illustrate improved 50% delay and rise time estimates when compared to traditional Elmore based two-pole models

HIGH PERFORMANCE CLOCK DISTRIBUTION FOR HIGH-SPEED VLSI SYSTEMS

Tohoku University堀口 進課

Effects of Temperature in Deep-Submicron Global Interconnect Optimization in Future Technology Nodes

The resistance of on-chip interconnects and the current drive of transistors are strongly temperature-dependent. As a result, the interconnect performance in Deep-Submicron technologies is affected by temperature in a substantial proportion. In this paper we evaluate thermal effects in global RLC interconnects and quantify their impact in a standard optimization procedure based on repeaters insertion. By evaluating the difference between a simple RC and an accurate RLC model, we show how the temperature induced increase of resistance may reduce the impact of inductance. We also project the evolution of such effects in future CMOS technologies, according to the semiconductor roadmap

SIGNAL PROCESSING TECHNIQUES AND APPLICATIONS

As the technologies scaling down, more transistors can be fabricated into the same area, which enables the integration of many components into the same substrate, referred to as system-on-chip (SoC). The components on SoC are connected by on-chip global interconnects. It has been shown in the recent International Technology Roadmap of Semiconductors (ITRS) that when scaling down, gate delay decreases, but global interconnect delay increases due to crosstalk. The interconnect delay has become a bottleneck of the overall system performance. Many techniques have been proposed to address crosstalk, such as shielding, buffer insertion, and crosstalk avoidance codes (CACs). The CAC is a promising technique due to its good crosstalk reduction, less power consumption and lower area. In this dissertation, I will present analytical delay models for on-chip interconnects with improved accuracy. This enables us to have a more accurate control of delays for transition patterns and lead to a more efficient CAC, whose worst-case delay is 30-40% smaller than the best of previously proposed CACs. As the clock frequency approaches multi-gigahertz, the parasitic inductance of on-chip interconnects has become significant and its detrimental effects, including increased delay, voltage overshoots and undershoots, and increased crosstalk noise, cannot be ignored. We introduce new CACs to address both capacitive and inductive couplings simultaneously.Quantum computers are more powerful in solving some NP problems than the classical computers. However, quantum computers suffer greatly from unwanted interactions with environment. Quantum error correction codes (QECCs) are needed to protect quantum information against noise and decoherence. Given their good error-correcting performance, it is desirable to adapt existing iterative decoding algorithms of LDPC codes to obtain LDPC-based QECCs. Several QECCs based on nonbinary LDPC codes have been proposed with a much better error-correcting performance than existing quantum codes over a qubit channel. In this dissertation, I will present stabilizer codes based on nonbinary QC-LDPC codes for qubit channels. The results will confirm the observation that QECCs based on nonbinary LDPC codes appear to achieve better performance than QECCs based on binary LDPC codes.As the technologies scaling down further to nanoscale, CMOS devices suffer greatly from the quantum mechanical effects. Some emerging nano devices, such as resonant tunneling diodes (RTDs), quantum cellular automata (QCA), and single electron transistors (SETs), have no such issues and are promising candidates to replace the traditional CMOS devices. Threshold gate, which can implement complex Boolean functions within a single gate, can be easily realized with these devices. Several applications dealing with real-valued signals have already been realized using nanotechnology based threshold gates. Unfortunately, the applications using finite fields, such as error correcting coding and cryptography, have not been realized using nanotechnology. The main obstacle is that they require a great number of exclusive-ORs (XORs), which cannot be realized in a single threshold gate. Besides, the fan-in of a threshold gate in RTD nanotechnology needs to be bounded for both reliability and performance purpose. In this dissertation, I will present a majority-class threshold architecture of XORs with bounded fan-in, and compare it with a Boolean-class architecture. I will show an application of the proposed XORs for the finite field multiplications. The analysis results will show that the majority class outperforms the Boolean class architectures in terms of hardware complexity and latency. I will also introduce a sort-and-search algorithm, which can be used for implementations of any symmetric functions. Since XOR is a special symmetric function, it can be implemented via the sort-and-search algorithm. To leverage the power of multi-input threshold functions, I generalize the previously proposed sort-and-search algorithm from a fan-in of two to arbitrary fan-ins, and propose an architecture of multi-input XORs with bounded fan-ins

Modeling and Analysis of Noise and Interconnects for On-Chip Communication Link Design

This thesis considers modeling and analysis of noise and interconnects in onchip communication. Besides transistor count and speed, the capabilities of a modern design are often limited by on-chip communication links. These links typically consist of multiple interconnects that run parallel to each other for long distances between functional or memory blocks. Due to the scaling of technology, the interconnects have considerable electrical parasitics that affect their performance, power dissipation and signal integrity. Furthermore, because of electromagnetic coupling, the interconnects in the link need to be considered as an interacting group instead of as isolated signal paths. There is a need for accurate and computationally effective models in the early stages of the chip design process to assess or optimize issues affecting these interconnects. For this purpose, a set of analytical models is developed for on-chip data links in this thesis. First, a model is proposed for modeling crosstalk and intersymbol interference. The model takes into account the effects of inductance, initial states and bit sequences. Intersymbol interference is shown to affect crosstalk voltage and propagation delay depending on bus throughput and the amount of inductance. Next, a model is proposed for the switching current of a coupled bus. The model is combined with an existing model to evaluate power supply noise. The model is then applied to reduce both functional crosstalk and power supply noise caused by a bus as a trade-off with time. The proposed reduction method is shown to be effective in reducing long-range crosstalk noise. The effects of process variation on encoded signaling are then modeled. In encoded signaling, the input signals to a bus are encoded using additional signaling circuitry. The proposed model includes variation in both the signaling circuitry and in the wires to calculate the total delay variation of a bus. The model is applied to study level-encoded dual-rail and 1-of-4 signaling. In addition to regular voltage-mode and encoded voltage-mode signaling, current-mode signaling is a promising technique for global communication. A model for energy dissipation in RLC current-mode signaling is proposed in the thesis. The energy is derived separately for the driver, wire and receiver termination.Siirretty Doriast

Analytic Delay Model of RLC Interconnects using Numerical Inversion of the Laplace Transform

Signal integrity analysis for on-chip interconnect becomes increasingly important in high-speed designs. SPICE, a conventional circuit simulator, can provide accurate prediction for interconnects, however, using SPICE is extremely computationally expensive. On the other hand, explicit moment matching technique can produce unstable poles for highly accurate approximations and implicit moment matching technique can obtain more accurate approximations at the expense of computational complexity. This thesis presents an analytic model to efficiently estimate the signal delays of RLC on-chip interconnects. It uses the numerical inversion of Laplace transform (NILT) to obtain time function, suitable for transient analysis. Since the integration formula of the NILT is numerically stable for higher order approximations, the developed algorithm provides a mechanism to increase the accuracy for delay estimation. Numerical examples are implemented and compared with HSPICE, two-pole model and Passive Reduced-Order Interconnect Macromodeling Algorithm (PRIMA) to illustrate the efficiency and validity of the proposed work

Investigation of Interconnect and Device Designs for Emerging Post-MOSFET and Beyond Silicon Technologies

Title from PDF of title page viewed May 31, 2017Dissertation advisor: Masud H. ChowdhuryVitaIncludes bibliographical references (pages 94-108)Thesis (Ph.D.)--School of Computing and Engineering and Department of Physics and Astronomy. University of Missouri--Kansas City, 2016The integrated circuit industry has been pursuing Moore’s curve down to deep nanoscale dimensions that would lead to the anticipated delivery of 100 billion transistors on a 300 mm² die operating below 1V supply in the next 5-10 years. However, the grand challenge is to reliably and efficiently take the full advantage of the unprecedented computing power offered by the billions of nanoscale transistors on a single chip. To mitigate this challenge, the limitations of both the interconnecting wires and semiconductor devices in integrated circuits have to be addressed. At the interconnect level, the major challenge in current high density integrated circuit is the electromagnetic and electrostatic impacts in the signal carrying lines. Addressing these problems require better analysis of interconnect resistance, inductance, and capacitance. Therefore, this dissertation has proposed a new delay model and analyzed the time-domain output response of complex poles, real poles, and double poles for resistance-inductance capacitance interconnect network based on a second order approximate transfer function. Both analytical models and simulation results show that the real poles model is much faster than the complex poles model, and achieves significantly higher accuracy in order to characterize the overshoot and undershoot of the output responses. On the other hand, the semiconductor industry is anticipating that within a decade silicon devices will be unable to meet the demands at nanoscale due to dimension and material scaling. Recently, molybdenum disulfide (MoS₂) has emerged as a new super material to replace silicon in future semiconductor devices. Besides, conventional field effect transistor technology is also reaching its thermodynamic limit. Breaking this thermal and physical limit requires adoption of new devices based on tunneling mechanism. Keeping the above mentioned trends, this dissertation also proposed a multilayer MoS₂ channel-based tunneling transistor and identifies the fundamental parameters and design specifications that need to be optimized in order to achieve higher ON-currents. A simple analytical model of the proposed device is derived by solving the time-independent Schrodinger equation. It is analytically proven that the proposed device can offer an ON-current of 80 A/m, a subthreshold swing (S) of 9.12 mV/decade, and a / ratio of 10¹².Introduction -- Previous models on interconnect designs -- Proposed delay model for interconnect design -- Investigation of tunneling for field effect transistor -- Study of molybdenum disulfide for FET applications -- Proposed molybdenum disulfide based tunnel transistor -- Conclusion -- Appendix A. Derivation of time delay model -- Appendix B. Derivation of tunneling current model Appendix C. Derivation of subthreshold swing mode