Minimizing End-to-End Delay and Maximizing Reliability using Multilayer Neural Network-based Hamming Back Propagation for Efficient Communication in WSN

Wireless sensor network (WSN) comprises number of spatially distributed sensor nodes for monitoring the physical environment conditions and arranging the gathered data at central location. WSN gained large attention in medical field, industry, military, etc. However, congestion control mechanism for communication between sensor nodes failed to consider the end-to-end delay features. In addition, it failed to handle reliability and not achieved the data concurrency. In order to address the above mentioned problems, Multilayer Neural Network-based Hamming Back Propagation (MNN-HBP) technique is introduced for efficient communication in WSN. In MNN-HBP technique, Amorphous View Point Algorithm is introduced for sensor node initialization for efficient communication in WSN. Amorphous View Point Algorithm used time of arrival to measure the time distance between the sender node and receiver node. After that Hamming Back Propagation Algorithm is used to identify the current location of the sensor nodes for minimizing the end-to end delay and improving the reliability. Each sensor node compares their distance with the neighbouring sensor nodes distance to identify the associated error. When the distance is higher, the associated error is higher and propagates error back to other sensor nodes in the previous layers. The process gets repeated until the communication established between source sensor and lower associated error nodes. By this way, efficient communication is carried out with higher reliability and minimum end-to end delay. Extensive simulation are conducted to illustrate the efficiency of proposed technique as well as the impacts of network parameters on end-to-end delay, reliability and data packets successful rate with respect to data packet size and number of data packets

Autonomously Reconfigurable Artificial Neural Network on a Chip

Artificial neural network (ANN), an established bio-inspired computing paradigm, has proved very effective in a variety of real-world problems and particularly useful for various emerging biomedical applications using specialized ANN hardware. Unfortunately, these ANN-based systems are increasingly vulnerable to both transient and permanent faults due to unrelenting advances in CMOS technology scaling, which sometimes can be catastrophic. The considerable resource and energy consumption and the lack of dynamic adaptability make conventional fault-tolerant techniques unsuitable for future portable medical solutions. Inspired by the self-healing and self-recovery mechanisms of human nervous system, this research seeks to address reliability issues of ANN-based hardware by proposing an Autonomously Reconfigurable Artificial Neural Network (ARANN) architectural framework. Leveraging the homogeneous structural characteristics of neural networks, ARANN is capable of adapting its structures and operations, both algorithmically and microarchitecturally, to react to unexpected neuron failures. Specifically, we propose three key techniques --- Distributed ANN, Decoupled Virtual-to-Physical Neuron Mapping, and Dual-Layer Synchronization --- to achieve cost-effective structural adaptation and ensure accurate system recovery. Moreover, an ARANN-enabled self-optimizing workflow is presented to adaptively explore a "Pareto-optimal" neural network structure for a given application, on the fly. Implemented and demonstrated on a Virtex-5 FPGA, ARANN can cover and adapt 93% chip area (neurons) with less than 1% chip overhead and O(n) reconfiguration latency. A detailed performance analysis has been completed based on various recovery scenarios

Advanced photonic and electronic systems - WILGA 2017

WILGA annual symposium on advanced photonic and electronic systems has been organized by young scientist for young scientists since two decades. It traditionally gathers more than 350 young researchers and their tutors. Ph.D students and graduates present their recent achievements during well attended oral sessions. Wilga is a very good digest of Ph.D. works carried out at technical universities in electronics and photonics, as well as information sciences throughout Poland and some neighboring countries. Publishing patronage over Wilga keep Elektronika technical journal by SEP, IJET by PAN and Proceedings of SPIE. The latter world editorial series publishes annually more than 200 papers from Wilga. Wilga 2017 was the XL edition of this meeting. The following topical tracks were distinguished: photonics, electronics, information technologies and system research. The article is a digest of some chosen works presented during Wilga 2017 symposium. WILGA 2017 works were published in Proc. SPIE vol.10445

Network-on-Chip Synchronization

Technology scaling has enabled the number of cores within a System on Chip (SoC) to increase significantly. Globally Asynchronous Locally Synchronous (GALS) systems using Dynamic Voltage and Frequency Scaling (DVFS) operate each of these cores on distinct and dynamic clock domains. The main communication method between these cores is increasingly more likely to be a Network-on-Chip (NoC). Typically, the interfaces between these clock domains experience multi-cycle synchronization latencies due to their use of “brute-force” synchronizers. This dissertation aims to improve the performance of NoCs and thereby SoCs as a whole by reducing this synchronization latency. First, a survey of NoC improvement techniques is presented. One such improvement technique: a multi-layer NoC, has been successfully simulated. Given how one of the most commonly used techniques is DVFS, a thorough analysis and simulation of brute-force synchronizer circuits in both current and future process technologies is presented. Unfortunately, a multi-cycle latency is unavoidable when using brute-force synchronizers, so predictive synchronizers which require only a single cycle of latency have been proposed. To demonstrate the impact of these predictive synchronizer circuits at a high level, multi-core system simulations incorporating these circuits have been completed. Multiple forms of GALS NoC configurations have been simulated, including multi-synchronous, NoC-synchronous, and single-synchronizer. Speedup on the SPLASH benchmark suite was measured to directly quantify the performance benefit of predictive synchronizers in a full system. Additionally, Mean Time Between Failures (MTBF) has been calculated for each NoC synchronizer configuration to determine the reliability benefit possible when using predictive synchronizers

A model of a distributed operating system

In this paper a logical model of a distributed operating system has been presented. This model of a distributed operating system contains a set of processes managing resources, connections between these processes, and mappings of events controlling this distributed operating system into processes managing resources. The fundamental types of resources introduced by the architecture of local computer networks, i.e., messages and data structures describing the location of resources in the network, have been defined. Operations on these resources and connections between the processes managing them and processes managing other resources of the distributed operating system have been presented. Addressing processes have been discussed. The model has been constructed in such a way that a synthesis of different simulation tools (models) to study distributed operating systems can be carried out. In particular, this model makes it possible to construct simulation tools to study the effectiveness of distributed operating systems with processes managing resources defined in different ways.That means that the model has been developed in such a way to be both a concept and a tool like the model developed by A. K. Jones. The later was treated by us as a background model