Compressed Passive Macromodeling

This paper presents an approach for the extraction of passive macromodels of large-scale interconnects from their frequency-domain scattering responses. Here, large scale is intended both in terms of number of electrical ports and required dynamic model order. For such structures, standard approaches based on rational approximation via vector fitting and passivity enforcement via model perturbation may fail because of excessive computational requirements, both in terms of memory size and runtime. Our approach addresses this complexity by first reducing the redundancy in the raw scattering responses through a projection and approximation process based on a truncated singular value decomposition. Then we formulate a compressed rational fitting and passivity enforcement framework which is able to obtain speedup factors up to 2 and 3 orders of magnitude with respect to standard approaches, with full control over the approximation errors. Numerical results on a large set of benchmark cases demonstrate the effectiveness of the proposed techniqu

Adaptive transient solution of nonuniform multiconductor transmission lines using wavelets

Abstract—This paper presents a highly adaptive algorithm for the transient simulation of nonuniform interconnects loaded with arbitrary nonlinear and dynamic terminations. The discretization of the governing equations is obtained through a weak formula-tion using biorthogonal wavelet bases as trial and test functions. It is shown how the multiresolution properties of wavelets lead to very sparse approximations of the voltages and currents in typical transient analyzes. A simple yet effective time–space adaptive al-gorithm capable of selecting the minimal number of unknowns at each time iteration is described. Numerical results show the high degree of adaptivity of the proposed scheme. Index Terms—Electromagnetic (EM) transient analysis, multi-conductor transmission lines (TLs), wavelet transforms. I

Parallel Algorithms for Time and Frequency Domain Circuit Simulation

As a most critical form of pre-silicon verification, transistor-level circuit simulation is an indispensable step before committing to an expensive manufacturing process. However, considering the nature of circuit simulation, it can be computationally expensive, especially for ever-larger transistor circuits with more complex device models. Therefore, it is becoming increasingly desirable to accelerate circuit simulation. On the other hand, the emergence of multi-core machines offers a promising solution to circuit simulation besides the known application of distributed-memory clustered computing platforms, which provides abundant hardware computing resources. This research addresses the limitations of traditional serial circuit simulations and proposes new techniques for both time-domain and frequency-domain parallel circuit simulations. For time-domain simulation, this dissertation presents a parallel transient simulation methodology. This new approach, called WavePipe, exploits coarse-grained application-level parallelism by simultaneously computing circuit solutions at multiple adjacent time points in a way resembling hardware pipelining. There are two embodiments in WavePipe: backward and forward pipelining schemes. While the former creates independent computing tasks that contribute to a larger future time step, the latter performs predictive computing along the forward direction. Unlike existing relaxation methods, WavePipe facilitates parallel circuit simulation without jeopardizing convergence and accuracy. As a coarse-grained parallel approach, it requires low parallel programming effort, furthermore it creates new avenues to have a full utilization of increasingly parallel hardware by going beyond conventional finer grained parallel device model evaluation and matrix solutions. This dissertation also exploits the recently developed explicit telescopic projective integration method for efficient parallel transient circuit simulation by addressing the stability limitation of explicit numerical integration. The new method allows the effective time step controlled by accuracy requirement instead of stability limitation. Therefore, it not only leads to noticeable efficiency improvement, but also lends itself to straightforward parallelization due to its explicit nature. For frequency-domain simulation, this dissertation presents a parallel harmonic balance approach, applicable to the steady-state and envelope-following analyses of both driven and autonomous circuits. The new approach is centered on a naturally-parallelizable preconditioning technique that speeds up the core computation in harmonic balance based analysis. The proposed method facilitates parallel computing via the use of domain knowledge and simplifies parallel programming compared with fine-grained strategies. As a result, favorable runtime speedups are achieved

Parallel numerical methods for large-scale DAE systems

For plantwide dynamic simulation in chemical process industry, parallel numerical methods using a divide and conquer strategy are considered. An approach for the numerical solution of initial value problems for large systems of differential algebraic equations (DAEs) arising from industrial applications and its realization on parallel computers with shared memory is discussed. The system is partitioned into blocks and then it is extended appropriately, such that block-structured Newton-type methods can be applied which enable the application of relaxation techniques. This approach has gained considerable speedup factors for the dynamic simulation of various large-scale distillation plants, covering systems with up to 60 000 equations

Modeling and Simulation of Nonlinearly Loaded Electromagnetic Systems via Reduced Order Models - A Case Study: Energy Selective Surfaces

L'abstract è presente nell'allegato / the abstract is in the attachmen

Signal Delay in General RC Networks with Application to Timing Simulation of Digital Integrated Circuits

Modeling digital MOS circuits by RC networks has become a well accepted practice for estimating delays. In 1981, Penfield and Rubinstein proposed a method to bound the waveforms of nodes in an RC tree network. In this paper, a single value of delay is derived for any node in a general RC network. The effects of parallel connections and stored charges are properly taken into consideration. The algorithms can be used either as a stand-alone simulator, or as a front end for producing initial waveforms for waveform-relaxation based circuit simulators. An experimental simulator called SDS (Signal Delay Simulator) has been developed. For all the examples tested so far, this simulator runs two to three orders of magnitude faster than SPICE, and detects all transitions and glitches at approximately the correct time

Behavioural simulation of mixed analogue/digital circuits.

Continuing improvements in integrated circuit technology have made possible the implementation of complex electronic systems on a single chip. This often requires both analogue and digital signal processing. It is essential to simulate such IC's during the design process to detect errors at an early stage. Unfortunately, the simulators that are currently available are not well-suited to large mixed-signal circuits. This thesis describes the design and development of a new methodology for simulating analogue and digital components in a single, integrated environment. The methodology represents components as behavioural models that are more efficient than the circuit models used in conventional simulators. The signals that flow between models are all represented as piecewise-linear (PWL) waveforms. Since models representing digital and analogue components use the same format to represent their signals, they can be directly connected together. An object-oriented approach was used to create a class hierarchy to implement the component models. This supports rapid development of new models since all models are derived from a common base class and inherit the methods and attributes defined in their parentc lassesT. he signal objectsa re implementedw ith a similar class hierarchy. The development and validation of models representing various digital, analogue and mixed-signal components are described. Comparisons are made between the accuracy and performance of the proposed methodology and several commercial simulators. The development of a Windows-based demonstrations imulation tool called POISE is also described. This permitted models to be tested independently and multiple models to be connected together to form structural models of complex circuits

Custom Integrated Circuits

Contains reports on nine research projects.Analog Devices, Inc.International Business Machines, Inc.Joint Services Electronics Program (Contract DAALO03-86-K-0002)U.S. Air Force - Office of Scientific Research (Grant AFOSR 86-0164)Rockwell International CorporationOKI SemiconductorU.S. Navy - Office of Naval Research (Contract N00014-81-K-0742)Charles Stark Draper LaboratoryDARPA/U.S. Navy - Office of Naval Research (Contract N00014-80-C-0622)DARPA/U.S. Navy - Office of Naval Research (Contract N00014-87-K-0825)National Science Foundation (Grant ECS-83-10941)AT&T Bell Laboratorie