Discrete-Time receivers for software-defined radio: challenges and solutions

Abstract—CMOS radio receiver architectures, based on radio frequency (RF) sampling followed by discrete-time (DT) signal processing via switched-capacitor circuits, have recently been proposed for dedicated radio standards. This paper explores the suitability of such DT receivers for highly flexible softwaredefined radio (SDR) receivers. Via symbolic analysis and simulations we analyze the properties of DT receivers, and show that at least three challenges exist to make a DT receiver work for SDR: 1) the sampling clock frequency is related to the radio frequency, complicating baseband filter design; 2) a frequencydependent phase shift is introduced by pseudo-quadrature and pseudo-differential sampling; 3) the conversion gain of a charge sampling front-end is strongly frequency-dependent. Some potential solutions are also suggested for each challenge. Compared to a mixer based radio receiver, extra costs are needed to solve these problems

Behavioral modeling for sampling receiver and baseband in Software-Defined Radio

Projecte realitzat en col.laboració amb Illinois Institute of TechnologySoftware Defined-Radio (SDR) consists of a wireless communication in which the transmitter and the receiver are controlled by means of software. Its ultimate goal is to provide a single universal radio transceiver capable of multi-mode multi-standard wireless communications. Modeling of the proper circuits and new designs aimed at SDR is necessary for further development and experimentation. It sharpens our understanding of fundamental processes, helps to make decisions and provides a guide for training exercises. Due to the lack of these models two independent and different models have been created based on new proposed designs. Each modeled design belongs to a different layer of abstraction and therefore, the tool used is different as well. The first proposed model consist of a Simulink (Matlab) file which models the discrete-time signal processing used in a Discrete-time receiver for Bluetooth Radio. The results show good performance when processing a signal that has been transmitted through a noisy channel. The signal at each step is visualized to see the individual effect of each building block. The second proposed model narrows down the topic and focuses on a Widely-tunable, Reconfigurable Analog Baseband filter, for which a Verilog-A model, by using Cadence, has been created. The outstanding feature of the filter is that its programmability is based on the duty-cycle of the input control signals. Moreover, Verilog-A modules bring the design really close to the real circuit, allowing the designer to face problems that the real circuit will present and easing the replacement of the building blocks with new ones when desired. The results for this model show a very little error within the passband of the filter that increases when the attenuation introduced for the stopband becomes higher

Joint synchronization and calibration of multi-channel transform-domain charge sampling receivers

Transform-domain (TD) sampling is seen as a potential candidate for wideband and ultra-wideband high-performance receivers and is investigated in detail in this research. TD receivers expand the signal over a set of basis functions and operate on the digitized basis coefficients. This parallel digital signal processing relaxes the sampling requirements opening the doors to higher dynamic range and wider bandwidth in receivers. This research is focused on the implementation of a high performance multi-channel wideband receiver that is based on Frequency-domain (FD) sampling, a special case of TD sampling. To achieve high dynamic ranges in these receivers, it is critical that the digital post processing block matches the analog RF front end accurately. This accurate matching has to be ensured across several process variations, mismatches and o�sets that can be present in integrated circuit implementations. A unified model has been defined for the FD multi-channel receiver that contains all these imperfections and a joint synchronization and calibration technique, based on the Least-mean-squared (LMS) algorithm, is presented to track them. A maximum likelihood (ML) algorithm is used to estimate the frequency offset in carriers which is corrected prior to LMS calibration. Simulation results are provided to support these concepts. The sampling circuits in FD receivers are based on charge-sampling and a multi-channel charge-sampling receiver creates an inherent sinc filter-bank that has several advantages compared to the conventional analog filter banks used in other multi-channel receivers. It is shown that the sinc filter banks, besides reduced analog complexity, have very low computational complexity in data estimation which greatly reduces the digital power consumption of these filters. The digital complexity of data estimation in the sinc fiter bank is shown to be less than 1=10th of the complexity in analog filter banks

Design and Implementation of FPGA based linear All Digital Phase-Locked Loop for Signal Processing Applications

This project presents a linear all-digital phase locked loop based on FPGA. In this ADPLL the phase detection system is realized by generating an analytic signal using a compact implementation of Hilbert transform and then simply computing the instantaneous phase using CORDIC algorithm in vectoring mode of operation. A 16-bit pipelined CORDIC algorithm is employed in order to obtain the phase information of the signal. All the components used in this phase detection system are realized as digital discrete time components. This design does not involve any class of multipliers thus reducing the complexity of the design. The loop filter of the ADPLL has been designed using PI controller which has a low pass behavior and is used to discard the higher order harmonics of the error signal. The CORDIC algorithm in its rotation mode of operation is used to compute sinusoidal values for the DDS. The ADPLL model has been implemented using Xilinx ISE 12.3 and ModelSim PE Student Edition 10.1a. The ADPLL model describes a novel method of implementation of CORDIC algorithm for the DDS system. This ADPLL model basically used for synchronization of closed loop RF control signals in a heavy ion particle accelerator can be implemented even in an ASIC which can be seen with a more general use for many a applications in the daily life

Implementation of a 1GHZ frontend using transform domain charge sampling techniques

The recent popularity and convenience of Wireless communication and the need for integration demands the development of Software Defined Radio (SDR). First defined by Mitoal, the SDR processed the entire bandwidth using a high resolution and high speed ADC and remaining operations were done in DSP. The current trend in SDRs is to design highly reconfigurable analog front ends which can handle narrow-band and wideband standards, one at a time. Charge sampling has been widely used in these architectures due to the built in antialiasing capabilities, jitter robustness at high signal frequencies and flexibility in filter design. This work proposed a 1GHz wideband front end aimed at SDR applications using Transform Domain (TD) sampling techniques. Frequency Domain (FD) sampling, a special case of TD sampling, efficiently parallelizes the signal for digital processing, relaxing the sampling requirements and enabling parallel digital processing at a much lower rate and is a potential candidate for SDR. The proposed front end converts the RF signal into current and then it is downconverted using passive mixers. The front end has five parallel paths, each acting on a part of the spectrum effectively parallelizing the front end and relaxing the requirements. An overlap introduced between successive integration windows for jitter robustness was exploited to create a novel sinc2 downsample by two filter topology. This topology was compared to a conventional topology and found to be equivalent and area efficient by about 44%. The proposed topology was used as a baseband filter for all paths in the front end. The chip was sent for fabrication in 45nm technology. The active area of the chip was 6:6mm2. The testing and measurement of the chip still remains to be done