Design of Low-Voltage Digital Building Blocks and ADCs for Energy-Efficient Systems

Increasing number of energy-limited applications continue to drive the demand for designing systems with high energy efficiency. This tutorial covers the main building blocks of a system implementation including digital logic, embedded memories, and analog-to-digital converters and describes the challenges and solutions to designing these blocks for low-voltage operation

An energy efficient sub-threshold baseband processor architecture for pulsed ultra-wideband communications

Thesis (S.M.)--Massachusetts Institute of Technology, Dept. of Electrical Engineering and Computer Science, 2006.Includes bibliographical references (p. 79-83).Ultra-wideband (UWB) communications is currently being explored as a medium for high-data-rate last-meter wireless links. Accordingly, there has been much interest in integrating UWB radios onto battery-operated devices, creating a strong demand for energy efficient UWB systems. The objective of this work is to describe how operating the digital baseband processor in the sub-threshold region and increasing the degree of parallelism can translate into energy savings across the entire UWB receiver. While sub-threshold operation is traditionally used for low energy, low performance applications such as wrist-watches, this work examines how sub-threshold operation can be applied to low energy, high performance applications. Simulation results for a 100-Mbps UWB baseband processor using the digital logic cell library of a 90-nm process are presented.by Vivienne Sze.S.M

An energy optimal power supply for digital circuits

Thesis (S.M.)--Massachusetts Institute of Technology, Dept. of Electrical Engineering and Computer Science, 2006.Includes bibliographical references (p. 96-98).The energy efficiency of digital circuits continues to be a major factor in determining the size and weight of battery-operated electronics. Integration of more functionality in a single system has made battery longevity a major problem. Operating circuits at their minimum energy operating voltage (MEP) has been proposed as a solution for energy critical applications where performance is not a key constraint. This thesis explores the sensitivity of the MEP to operating conditions and motivates the need for continuous minimum energy tracking based on the energy savings possible. A circuit that can dynamically track the MEP of a digital circuit with varying load conditions and temperature is presented. A low power, voltage scalable DC-DC converter is also embedded within the chip. The proposed minimum energy tracking algorithm uses a novel approach to sense the energy consumed per operation. The energy sensing circuitry does not use high-resolution Analog-to-Digital converters or high gain amplifiers. The energy estimate is used in a slope tracking algorithm to track the minimum energy operating voltage. The minimum energy tracking loop along with a low-voltage DC-DC converter and test circuitry were fabricated in a 65nm CMOS process.(cont.) The circuits are powered from an external 1.2V supply. The digital test circuitry was capable of operation at voltages as low as 0.25V. The tracking of the minimum energy operating voltage with change in workload and temperature was observed. The DC-DC converter was able to deliver load voltages between 0.25V and 0.7V with an efficiency > 78% at load power levels of the order of 1 0.1W and above.by Yogesh Kumar Ramadass.S.M

Design, analysis and implementation of voltage sensor for power-constrained systems

PhD ThesisThanks to an extensive effort by the global research community, the electronic technology has significantly matured over the last decade. This technology has enabled certain operations which humans could not otherwise easily perform. For instance, electronic systems can be used to perform sensing, monitoring and even control operations in environments such as outer space, underground, under the sea or even inside the human body. The main difficulty for electronics operating in these environments is access to a reliable and permanent source of energy. Using batteries as the immediate solution for this problem has helped to provide energy for limited periods of time; however, regular maintenance and replacement are required. Consequently, battery solutions fail wherever replacing them is not possible or operation for long periods is needed. For such cases, researchers have proposed harvesting ambient energy and converting it into an electrical form. An important issue with energy harvesters is that their operation and output power depend critically on the amount of energy they receive and because ambient energy often tends to be sporadic in nature, energy harvesters cannot produce stable or fixed levels of power all of the time. Therefore, electronic devices powered in this way must be capable of adapting their operation to the energy status of the harvester. To achieve this, information on the energy available for use is needed. This can be provided by a sensor capable of measuring voltage. However, stable and fixed voltage and time references are a prerequisite of most traditional voltage measurement devices, but these generally do not exist in energy harvesting environments. A further challenge is that such a sensor also needs to be powered by the energy harvester’s unstable voltage. In this thesis, the design of a reference-free voltage sensor, which can operate with a varying voltage source, is provided based on the capture of a portion of the total energy which is directly related to II the energy being sensed. This energy is then used to power a computation which quantifies captured energy over time, with the information directly generated as digital code. The sensor was fabricated in the 180 nm technology node and successfully tested by performing voltage measurements over the range 1.8 V to 0.8 V

A sub-threshold cell library and methodology

Thesis (S.M.)--Massachusetts Institute of Technology, Dept. of Electrical Engineering and Computer Science, 2006.Includes bibliographical references (p. 97-102).Sub-threshold operation is a compelling approach for energy-constrained applications where speed is of secondary concern, but increased sensitivity to process variation must be mitigated in this regime. With scaling of process technologies, random within-die variation has recently introduced another degree of complexity in circuit design. This thesis proposes approaches to mitigate process variation in sub-threshold circuits through device sizing, topology selection and fault-tolerant architecture. This thesis makes several contributions to a sub-threshold circuit design methodology. A formal analysis of device sizing trade-offs between delay, energy, and variability reveals that while minimum size devices provide lowest energy and delay in sub-threshold, their increased sensitivity to random dopant fluctuation may cause functional errors. A proposed variation-driven design approach enables consistent sizing of logic gates and registers for constant functional yield. A yield constraint imposes energy overhead at low power supply voltages and changes the minimum energy operating point of a circuit.(cont.) The optimal supply and device sizing depend on the topology of the circuit and its energy versus VDD characteristic. The analysis resulted in a 56-cell library in 65nm CMOS, which is incorporated in a computer-aided design flow. A test chip synthesized from this library implements a fault-tolerant FIR filter. Algorithmic error detection enables correction of transient timing errors due to delay variability in sub-threshold, and also allows the system frequency to be set more aggressively for the average case instead of the worst case.by Joyce Y.S. Kwong.S.M

Análise automática da operação a tensões sub-limiares em circuitos digitais CMOS

The Internet of Things (IoT) paradigm is enabling easy access and interaction with a wide variety of devices, some of them self-powered, equipped with microcontrollers, sensors and sensor networks. Low power and ultra-low-power strategies, as never before, have a huge importance in today’s CMOS integrated circuits, as all portable devices quest for the never-ending battery life, but also with smaller and smaller dimensions every day. The solution is to use clever power management strategies and reduce drastically power consumption in IoT chips. Dynamic Voltage and Frequency Scaling techniques can be rewardingly, and using operation at subthreshold power-supply voltages can effectively achieve significant power savings. However, reducing power-supply voltages impose reduction of performance and, consequently, delay increase, in turn it makes the circuit more vulnerable to operational-induced delay-faults and transientfaults. What is the best compromise between power, delay and performance? This thesis proposes an automatic methodology and tool to perform power-delay analysis in CMOS gates and circuits, to identify automatically the best compromise between power and delay. By instantiating SPICE simulator, the proposed tool can automatically perform analysis such as: power-delay product, energy-delay product, power dissipation, or even dynamic and static power dissipations. The optimum operation point in respect to the power-supply voltage is defined, for each circuit or sub-circuit and considering subthreshold operation or not, to the minimum power-supply voltage where the delays do not increase too much and that implements a compromise between delay and power consumption. The algorithm is presented, along with CMOS circuit examples, all the analysis’ results are shown for typical benchmark circuits. Results indicate that subthreshold voltages can be a good compromise in reducing power and increasing delays.O aparecimento e a expansão de novas tendências da indústria electrónica fortemente direccionadas ao paradigma da Internet of Things (IoT) têm vindo a dar uma relevância cada vez maior à necessidade da evolução da electrónica, no sentido da interligação e intercomunicação entre equipamentos, no sentido da miniaturização em geral e, consequentemente, no sentido de uma melhor eficiência energética. Temos assim, na prática, vindo recentemente a assistir em diversas áreas ao surgimento progressivo de um número exponencial de pequenos dispositivos electrónicos, altamente compactos, com elevado grau de integração de funções e habitualmente interligados entre si em redes de dados. Habitualmente têm como missão genérica a recolha, processamento e transmissão de dados acerca do ambiente que os rodeia. Esta grande variedade de diferentes dispositivos habitualmente relacionados ao campo de IoT tem como principais funções a recolha e transdução de dados obtidos do ambiente circundante por sensores. Tem por isso geralmente uma muito limitada interação com o ambiente circundante, e nesse sentido, justifica-se que as suas principais características sejam as pequenas dimensões e fácil portabilidade. Justifica-se também que não é estritamente essencial que tenham elevada performance a nível de processamento. Sendo alimentados por baterias, ou nalguns casos alimentados por energia do ambiente, estes dispositivos precisam obrigatoriamente de consumir muito pouca energia, sendo os seus requisitos de energia de alimentação muito restritos. Dados os restritos requisitos de consumo energético, são tipos de circuitos muito adequados à aplicação das mais recentes e avançadas estratégias de gestão de potência destinadas a reduzir drasticamente a potência nos modernos circuitos integrados CMOs. Torna-se assim claro, que os mais importantes requisitos futuros de dispositivos na área de IoT, assim como de diversas famílias de dispositivos electrónicos em geral, serão tendencialmente a necessidade de redução de consumo energético, ainda que esta redução seja feita à custa de algum nível de redução em performance. Esta tendência baseia-se no crescimento de importância da temática da eficiência energética em circuitos, num momento em que a concentração de consumo energético e consequentemente de dissipação térmica, em áreas muito reduzidas de circuitos integrados CMOs atinge níveis muito elevados e preocupantes. Uma possível solução para enfrentar este complexo desafio, com crescentes requisitos e restrições para actuais e futuros circuitos CMOs, tendo em atenção princípios globais de eficiência energética, consiste em conjugar as habituais técnicas de gestão de potência dinâmica em circuitos, com as mais recentes e avançadas técnicas de alimentação em ‘ultra-low-power voltage’, tentando alcançar assim ganhos de potência muito consideráveis e significativos. Assim, associando as conhecidas técnicas de gestão de potência como por exemplo a Dynamic Voltage and Frequency Scaling (DVFS) com as mais recentes técnicas de ultra-low-power voltage como a recente técnica de operação em tensões de alimentação subthreshold pode potencialmente se revelar como a melhor solução para enfrentar este complexo problema e assim melhorar significativamente a eficiência energética em futuros circuitos CMOS. Contudo, quando aplicamos técnicas de potência de very-low-power ou ultra-lowpower, como as técnicas de operação a tensões subthreshold, existem algumas desvantagens e alguns efeitos adversos que devem ser cuidadosamente considerados e, se possível, contidos e minimizados. A mais importante destas consequências directas é a perda de performance do circuito que deriva naturalmente do aumento nos atrasos de propagação internos do circuito. As restantes desvantagens da utilização de técnicas de alimentação a níveis muito baixos derivam todas elas do facto do circuito se tornar em geral muito mais sensível a perturbações internas ou externas. Esta é claramente uma consequência natural para uma operação a este nível de reduzida energia. Como seria de esperar, pelo exposto, a operação a níveis de tensão ultra-low-voltage têm a consequência de torná-lo mais sensível a distúrbios e interferências, aumentado assim o risco de falhas operacionais, dado que o nível dos seus sinais internos de operação ao longo do circuito é muito reduzido. Alguns efeitos adversos afectos ao uso de técnicas de ultra-low-power em circuitos CMOs incluem, portanto, o aumento da vulnerabilidade do circuito a Single Event Upsets (SEUs), incluem também o aumento de vulnerabilidade a falhas induzidas de delay de operação, assim como um aumento de sensibilidade do circuito a falhas geradas por transientes. Tendo consciência do incremento de riscos operacionais envolvido em circuitos subthreshold, são necessários cuidados no sentido de conter e minimizar tanto quanto possíveis efeitos indesejados, por exemplo controlando cuidadosamente as condições operacionais do circuito e melhorando a sua blindagem a interferências. Considerando que o uso das técnicas de ultra-low-power pode ser provavelmente a melhor solução para cumprir rigorosos requisitos de eficiência energética para um circuito CMOs, é necessário considerar também que estas técnicas podem gerar uma considerável perda de performance, traduzida por um maior atraso interno. Assim, torna-se necessário estudar claramente, em subthreshold voltages, a evolução da perda de performance face aos grandes ganhos de energia quando caminhamos no sentido da redução da tensão de alimentação de um circuito CMO’s. Tendo como base um estudo custo/benefício da evolução de dois factores cruciais na operação de um circuito, como o factor energia e o factor performance, torna-se possível tentar alcançar uma solução de compromisso entre a potência dissipada (energia consumida) e o atraso de propagação, traduzido como a performance do circuito. O trabalho aqui apresentado propõe uma metodologia automatizada, capaz de enfrentar os desafios do estudo mencionado. Propõe ainda uma ferramenta de software desenhada para analisar em detalhe portas lógicas CMOs de uma livraria de portas existente, assim como circuitos completos composto por diversas portas lógicas. O software proposto analisa um circuito ou sub-circuito lógico, identificando automaticamente o melhor nível de alimentação de baixa tensão (ponto de operação óptimo) que permite obter o melhor compromisso entre potência e atraso, em termos gerais o melhor compromisso entre energia e performance. Como suporte e assistência à metodologia proposta esta ferramenta foi criada para acelerar os testes de simulação Hspice sobre portas lógicas e circuitos, executando cálculos rápidos sobre resultados de simulação e acelerando a obtenção de resultados de eficiência energética e de performance para análise. Através da instanciação directa do simulador Hspice, a ferramenta facilita a análise de importantes parâmetros de definição de portas lógicas e circuitos, como por exemplo: o atraso de propagação, o power-delay-product (PDP), o energy-delay-product (EDP), e a dissipação de potência total e parcial (estática e dinâmica). O desenvolvimento inicial da ferramenta permitiu realizar múltiplos testes e simulações e através da análise destes resultados desenvolver a metodologia low-power apresentada no trabalho, a posterior aplicação da metodologia pela ferramenta a um circuito CMO’s permite eficientemente identificar o seu ponto de operação óptimo para operação em baixo nível. Um ponto de operação óptimo de uma porta lógica é definido pelo método como o mais baixo nível de tensão de alimentação que não compromete a operação válida da porta, reduzindo por isso fortemente a potência dissipada. No entanto este ponto deve ainda minimizar (tanto quanto possível) os atrasos de propagação na porta. Assim, este ponto deriva de um compromisso ponderado para uma alimentação com consumo de energia muito baixo, que contudo não gere ainda atrasos na porta que provoquem significativas perdas em performance. Acima de tudo, o trabalho desenvolvido pretende apresentar uma abordagem clara e directa ao design e implementação de lógica digital em modo de subthreshold, aplicado ao contexto dos modernos circuitos de electrónica digital. Pretende-se estabelecer um conjunto de técnicas e métodos simples e claros, suportados num estudo incidente em regras teóricas e em simulações prácticas, que possam servir como normativos propostos para o design de circuitos adaptados ao funcionamento em modos de muito baixa energia. O objectivo final será enfrentar e a longo prazo tentar resolver o problema cada vez maior e mais importante da melhoria de eficiência energética em circuitos electrónicos genéricos

Design and Implementation of a Low Power T-gate Cell Library and Comparison with Its Cmos Equivalent

This work presents the design methodologies, considerations and practical implementation techniques of a sub-threshold/ moderate inversion variability aware Transmission Gate based digital cell library. The implementation method of a reduced ASIC cell library containing minimum number of logic gates sufficient for further front end and back end processing is described. The proposed library targets a reduced implementation time and effort suitable for academic and industrial environment aiming minimum power consumption in battery less devices, portable electronic gadgets or wireless micro sensor networks where computation speed is not of prime concern. To the authors best knowledge, none of the literature till date demonstrates clearly and in a consolidated manner the applicability of T-Gate logic topology as a candidate for ultra-low power applications. Hence, a comparison is presented with equivalent low power CMOS logic gates. Circuit behavior can be significantly impacted due to MOSFET parameter variation. Clear simulation based measurement techniques are presented for measuring concerned parameters like input capacitance, Static Noise Margin(SNM) and IOFF of the T-Gate logic cells and compared with its CMOS equivalent at the same PVT corners. It is observed that the T-Gate shows lower normalized input capacitance than CMOS logic gates. A statistical analysis of logic failure is also presented along with its potential solutions for improvement. As compared to the CMOS gates, the T-Gate logic gates are found to demonstrate slightly narrower distribution of the switching threshold point(VTrip) when performed 200 point Monte Carlo simulation taking process variation and mismatch into account. The CMOS gates demonstrate better static noise margin and hence more robust than T-Gate logic cell and suitable for lower supply voltage operation. A comparison of IOFF is presented to compare the static behavior of the two topologies. The details of device and gate sizing methodology are described along with necessary references. The library is characterized and abstracted to generate necessary files for further processing. A target system is synthesized and a seven stage ring oscillator is simulated in both topologies and is compared to make conclusion based on the observations. T-Gate logic cells demonstrate better static behavior but outperformed by its CMOS logic equivalent in terms of energy consumed per cycle within the range of VDDD from 400mV to 600mV. T-Gate logic gates are slower than its CMOS counterpart at any VDDD of operation and insignificant improvement is achieved with increasing power supply.Electrical Engineerin

Wireless Transceivers for Implantable Microsystems.

In this thesis, we present the first-ever fully integrated mm3 low-power biomedical transceiver with 1 meter of range that is powered by a mm2 thin-film battery. The transceiver is targeted for biomedical implants where size and energy constraints dictated by application make design challenging. Despite all the previous work in RFID tags, form factor of such radios is incompatible with mm3 biomedical implants. The proposed transceiver bridges this gap by providing a compact low-power solution that can run off small thin-film batteries and can be stacked with other system components in a 3D fashion. On the sensor-to-external side, we proposed a novel FSK architecture based on dual-resonator LC oscillators to mitigate unwanted overlap of two FSK tones’ phase noise spectrum. Due to inherent complexity of such systems, fourth order dual-resonator oscillators can exhibit instable operation. We mathematically modeled the instability and derive design conditions for stable oscillations. Through simulation and measurements, validity of derived models was confirmed. Together with other low-power system blocks, the transmitter was successfully implanted in live mouse and in-vivo measurements were performed to confirm successful transmission of vital signals through organic tissue. The integrated transmitter achieved a bit-error-rate of 10-6 at 10cm with 4.7nJ/bit energy consumption. On the external-to-sensor link, we proposed a new protocol to lower receiver peak power, which is highly limited due to small size of mm3 microsystem battery. In the proposed protocol, sending same data multiple times drastically relaxes jitter requirement on the sensor side at the cost of increased power consumption on the external side without increasing peak power radiated by the external unit. The receiver also uses a dual-coil LNA to improve range by 22% with only 11% area overhead. An asynchronous controller manages protocol timing and limits total monitoring current to 43nA. The fabricated receiver consumes 1.6nJ/bit at 40kbps while positioned 1m away from a 2W source.PhDElectrical EngineeringUniversity of Michigan, Horace H. Rackham School of Graduate Studieshttp://deepblue.lib.umich.edu/bitstream/2027.42/102458/1/ghaed_1.pd

Power Analysis of Sub-threshold Logics for Security Applications

Requirements of ultra-low power for many portable devices have drawn increased attention to digital sub-threshold logic design. Major reductions in power consumption and frequency of operation degradation due to the exponential decrease of the drain current in the sub-threshold region has made this logic an excellent choice, particularly for ultra-low power applications where performance is not the primary concern. Examples include RFID, wireless sensor networks and biomedical implantable devices. Along with energy consumption, security is another compelling requirement for these applications. Power analysis attacks, such as Correlation Power Analysis (CPA), are a powerful type of side channel attacks that are capable of performing a non-invasive attack with minimum equipment. As such, they present a serious threat to devices with secret information inside. This research analyzes sub-threshold logics from a previously unexplored perspective, side channel information leakage. Various transistor level and RTL circuits are implemented in the sub-threshold region as well as in the strong inversion region (normally the standard region of operation) using a 65 nm process. Measures, such as Difference of Mean Energies (DME), Normalized Energy Deviation (NED) and Normalized Standard Deviation (NSD) are employed to evaluate the implemented architectures. A CPA attack is also performed on more complex designs and the obtained correlation coefficients are used to compare sub-threshold and strong inversion logics. This research demonstrates that sub-threshold does not only increase the security against side channel attacks, but can also decrease the amount of leaked information. This research also shows that a circuit operating at sub-threshold consumes considerably less energy than the same circuit operating in strong inversion and the level of its instantaneous power consumption is significantly lower. Therefore, the noise power required to cover the secret information decreases and the attack may be dramatically more difficult due to major increase in the number of required power traces and run time. Thus, this research is important for identifying sub-threshold as a future viable technology for secure embedded applications

Designing energy-efficient computing systems using equalization and machine learning

As technology scaling slows down in the nanometer CMOS regime and mobile computing becomes more ubiquitous, designing energy-efficient hardware for mobile systems is becoming increasingly critical and challenging. Although various approaches like near-threshold computing (NTC), aggressive voltage scaling with shadow latches, etc. have been proposed to get the most out of limited battery life, there is still no “silver bullet” to increasing power-performance demands of the mobile systems. Moreover, given that a mobile system could operate in a variety of environmental conditions, like different temperatures, have varying performance requirements, etc., there is a growing need for designing tunable/reconfigurable systems in order to achieve energy-efficient operation. In this work we propose to address the energy- efficiency problem of mobile systems using two different approaches: circuit tunability and distributed adaptive algorithms. Inspired by the communication systems, we developed feedback equalization based digital logic that changes the threshold of its gates based on the input pattern. We showed that feedback equalization in static complementary CMOS logic enabled up to 20% reduction in energy dissipation while maintaining the performance metrics. We also achieved 30% reduction in energy dissipation for pass-transistor digital logic (PTL) with equalization while maintaining performance. In addition, we proposed a mechanism that leverages feedback equalization techniques to achieve near optimal operation of static complementary CMOS logic blocks over the entire voltage range from near threshold supply voltage to nominal supply voltage. Using energy-delay product (EDP) as a metric we analyzed the use of the feedback equalizer as part of various sequential computational blocks. Our analysis shows that for near-threshold voltage operation, when equalization was used, we can improve the operating frequency by up to 30%, while the energy increase was less than 15%, with an overall EDP reduction of ≈10%. We also observe an EDP reduction of close to 5% across entire above-threshold voltage range. On the distributed adaptive algorithm front, we explored energy-efficient hardware implementation of machine learning algorithms. We proposed an adaptive classifier that leverages the wide variability in data complexity to enable energy-efficient data classification operations for mobile systems. Our approach takes advantage of varying classification hardness across data to dynamically allocate resources and improve energy efficiency. On average, our adaptive classifier is ≈100× more energy efficient but has ≈1% higher error rate than a complex radial basis function classifier and is ≈10× less energy efficient but has ≈40% lower error rate than a simple linear classifier across a wide range of classification data sets. We also developed a field of groves (FoG) implementation of random forests (RF) that achieves an accuracy comparable to Convolutional Neural Networks (CNN) and Support Vector Machines (SVM) under tight energy budgets. The FoG architecture takes advantage of the fact that in random forests a small portion of the weak classifiers (decision trees) might be sufficient to achieve high statistical performance. By dividing the random forest into smaller forests (Groves), and conditionally executing the rest of the forest, FoG is able to achieve much higher energy efficiency levels for comparable error rates. We also take advantage of the distributed nature of the FoG to achieve high level of parallelism. Our evaluation shows that at maximum achievable accuracies FoG consumes ≈1.48×, ≈24×, ≈2.5×, and ≈34.7× lower energy per classification compared to conventional RF, SVM-RBF , Multi-Layer Perceptron Network (MLP), and CNN, respectively. FoG is 6.5× less energy efficient than SVM-LR, but achieves 18% higher accuracy on average across all considered datasets