Characterization of 4H-SiC MOSFETs Using First Principles Coulomb Scattering Mobility Modeling and Device Simulation

Detailed analysis of a 4H-SiC MOSFET has been carried out by numerically solving the steady state semiconductor Drift-Diffusion equations. Mobility models for bulk phonon scattering, surface phonon scattering, surface roughness scattering, Coulomb scattering by interface traps and oxide charges, and high field effects, have been developed and implemented. A first principles Coulomb scattering mobility model has been developed specifically to model the physics of the inversion layer in 4H-SiC MOSFETs. The Coulomb scattering model takes into account, scattering of mobile charges by occupied interface traps and fixed oxide charges, distribution of mobile charges in the inversion layer, and screening. Simulated IV curves have been compared to experimental data. Density of states for the interface traps have been extracted, and seem to be in agreement with experimental measurements. Simulations indicate that occupied interface traps in 4H-SiC MOSFETs are responsible for mobility degradation, low currents and high threshold voltages. Their effect diminishes at high temperatures due to reduction in trap occupancy, and at high gate voltages due to increased screening. At high gate voltages, surface roughness scattering plays the major role in mobility degradation in 4H-SiC MOSFETs

Characterisation of silicon carbide CMOS devices for high temperature applications

PhD ThesisIn recent years it has become increasingly apparent that there is a large demand for resilient electronics that can operate within environments that standard silicon electronics cease to function such as high power and high voltage applications, high temperatures, corrosive atmospheres and environments exposed to radiation. This has become even more essential due to increased demands for sustainable energy production and the reduction in carbon emissions worldwide, which has put a large burden on a wide range of industrial sectors who now have a significant demand for electronics to meet these needs including; military, space, aerospace, automotive, energy and nuclear. In extreme environments, where ambient temperatures may well exceed the physical limit of silicon-based technologies, SiC based technology offers a lower cost and a smaller footprint solution for operation in such environments due to its advantageous electrical properties such as a high breakdown electric field, high thermal conductivity and large saturation velocity. High quality material on large area wafers (150 mm) is now commercially available, allowing the fabrication of reliable high temperature, high frequency and high current power electronic devices, improving the already optimised silicon based structures. An important advantage of SiC is that it is the only wide band gap compound semiconductor that can be thermally oxidised to grow insulating, high quality SiO2 layers, which makes it an ideal candidate to replace silicon technologies for metal-oxide-semiconductor applications, which is the main focus of this research. Although the technology has made a number of major steps forward over recent years and the commercial manufacturing process has advanced significantly, there still remains a number of issues that need to be overcome in order to fully realise the potential of the material for electronic applications. This thesis describes the characterisation of 4H-SiC CMOS structures that were designed for high temperature applications and fabricated with varying gate dielectric treatments and process steps. The influence of process techniques on the characteristics of metal-oxide-semiconductor (MOS) devices has been investigated by means of electrical characterisation and the results have been compared to theoretical models. The C-V and I-V characteristics of both MOS capacitor and MOSFET structures with varying gate dielectrics on both n-type and p-type 4H-SiC have been analysed to explore the benefits of the varying process techniques that have been employed in the design of the devices. The results show that the field effect mobility characteristic of 4H-SiC MOSFETs are dominated at low perpendicular electric fields by Coulomb scattering and at high electric fields by low surface roughness mobility, which is due to the rough SiC-SiO2 interface. The findings also show that a thermally grown SiO2 layer at the semiconductor-dielectric interface is a beneficial process step that enhances the interfacial characteristics and increases the channel mobility of the MOSFETs. In addition to this it is also found that this technique provides the most beneficial characteristics on both n-type and p-type 4H-SiC, which suggests that it would be the most suitable treatment for a monolithic CMOS process. The impact of threshold voltage adjust ion implantation on both the MIS capacitor and MOSFET structures is also presented and shows that the increasing doses of nitrogen that are implanted to adjust the threshold voltage act to improve the device performance by acting to modify the charge at the interface or within the gate oxide and therefore increase the field effect mobility of the studied devices.Engineering and Physical Sciences Research Council (EPSRC) and Raytheon U

Modeling and Characterization of 4H-SIC MOSFETs: High Field, High Temperature, and Transient Effects

We present detailed physics based numerical models for characterizing 4H-Silicon Carbide lateral MOSFETs and vertical power DMOSFETs for high temperature, high field, DC, AC and transient switching operating conditions. A complete 2-D Drift-Diffusion based device simulator has been developed specifically for SiC MOSFETs, to evaluate device performance in a variety of operating scenarios, and to extract relevant physical parameters. We have developed and implemented room and high temperature mobility models for bulk phonon and impurity scattering, surface phonon scattering, Coulomb scattering from interface traps, and surface roughness scattering. High temperature models for interface trap density of states and occupation probability of interface traps are also implemented. By rigorous comparison of simulated I-V characteristics to experimental data at high temperatures, physical parameters like interface trap density of states, surface step height, saturation velocity, etc. have been extracted. Insight into relative importance of scattering mechanisms influencing transport in SiC MOSFETs has been provided. We show that the strongest contribution to low current in SiC MOSFETs is from the loss of mobile inversion charge due to large amount of trapping at the interface, and due to very low surface mobility arising due to a rough SiC-SiO2 interface. We show that surface roughness scattering dominates at high gate biases and is the most important scattering mechanism in 4H-SiC MOSFETs. Switching characteristics of SiC lateral MOSFETs have been modeled and simulated using our custom device simulator. A comprehensive generation-recombination model for interaction between inversion layer electrons and interface traps has been developed. Using this model, we have modeled the time-dependent occupation of interface traps spread inside the SiC bandgap. We have measured the transient characteristics of these devices, and compare our simulation to experiment and have extracted capture cross-sections of interface traps. Using the coupled experiment and modeling approach, we are able to distinguish between fast interface traps and slow oxide traps, and explain how they contribute to threshold voltage instability. High power 4H-SiC DMOSFET operation in the ON and the OFF states has also been analyzed. We show that in current generation SiC DMOSFETs, the ON resistance is dominated by the channel resistance instead of the drift-layer resistance. This makes the design of SiC DMOSFETs far from ideal. OFF state blocking capability and breakdown due to impact ionization of the DMOSFETs are also modeled and simulated. We show that the 4H-SiC DMOSFETs have excellent leakage characteristics and can support extremely high OFF state drain voltages

Performance and robustness characterisation of SiC power MOSFETs

Over the last few years, significant advancements in the SiC power MOSFET fabrication technology has led to their wide commercial availability from various manufacturers. As a result, they have now transitioned from being a research activity to becoming an industrial reality. SiC power MOSFET technology offers great benefits in the electrical energy conversion domain which have been widely discussed and partially demonstrated. Superior material properties of SiC and the consequent advantages are both later discussed here. For any new device technology to be widely implemented in power electronics applications, it’s crucial to thoroughly investigate and then validate for robustness, reliability and electrical parameter stability requirements set by the industry. This thesis focuses on device characterisation of state-of-the-art SiC power MOSFETs from different manufacturers during short circuit and avalanche breakdown operation modes under a wide range of operating conditions. The functional characterisation of packaged DUTs was thoroughly performed outside of the safe operating area up until failure test conditions to obtain absolute device limitations. For structural characterisation, Infrared thermography on bare die DUTs was also performed with an aim to observe hotspots and/or degradation of the structural features of the device. The experimental results are also complemented by 2D TCAD simulation results in order to get a further insight into the underlying physical mechanisms behind failure during such operation regimes. Moreover, the DUTs were also tested for body diode characterisation with an aim to observe degradation and instability of electrical device parameters which may adversely affect the performance of the overall system. Such investigations are really important and act as a feedback to device manufacturers for further technological improvements in order to overcome the highlighted issues with an aim to bring about advancements in device design to meet the ever-increasing demands of power electronics

Performance and robustness characterisation of SiC power MOSFETs

Over the last few years, significant advancements in the SiC power MOSFET fabrication technology has led to their wide commercial availability from various manufacturers. As a result, they have now transitioned from being a research activity to becoming an industrial reality. SiC power MOSFET technology offers great benefits in the electrical energy conversion domain which have been widely discussed and partially demonstrated. Superior material properties of SiC and the consequent advantages are both later discussed here. For any new device technology to be widely implemented in power electronics applications, it’s crucial to thoroughly investigate and then validate for robustness, reliability and electrical parameter stability requirements set by the industry. This thesis focuses on device characterisation of state-of-the-art SiC power MOSFETs from different manufacturers during short circuit and avalanche breakdown operation modes under a wide range of operating conditions. The functional characterisation of packaged DUTs was thoroughly performed outside of the safe operating area up until failure test conditions to obtain absolute device limitations. For structural characterisation, Infrared thermography on bare die DUTs was also performed with an aim to observe hotspots and/or degradation of the structural features of the device. The experimental results are also complemented by 2D TCAD simulation results in order to get a further insight into the underlying physical mechanisms behind failure during such operation regimes. Moreover, the DUTs were also tested for body diode characterisation with an aim to observe degradation and instability of electrical device parameters which may adversely affect the performance of the overall system. Such investigations are really important and act as a feedback to device manufacturers for further technological improvements in order to overcome the highlighted issues with an aim to bring about advancements in device design to meet the ever-increasing demands of power electronics