Structural variants of biodegradable polyesterurethane in vivo evoke a cellular and angiogenic response that is dictated by architecture

This is the author's accepted manuscript. The final published article is available from the link below. Copyright @ 2008 Acta Materialia Inc.The aim of this study was to investigate an in vivo tissue response to a biodegradable polyesterurethane, specifically the cellular and angiogenic response evoked by varying implant architectures in a subcutaneous rabbit implant model. A synthetic biodegradable polyesterurethane was synthesized and processed into three different configurations: a non-porous film, a porous mesh and a porous membrane. Glutaraldehyde cross-linked bovine pericardium was used as a control. Sterile polyesterurethane and control samples were implanted subcutaneously in six rabbits (n = 12). The rabbits were killed at 21 and 63 days and the implant sites were sectioned and histologically stained using haemotoxylin and eosin (H&E), Masson’s trichrome, picosirius red and immunostain CD31. The tissue–implant interface thickness was measured from the H&E slides. Stereological techniques were used to quantify the tissue reaction at each time point that included volume fraction of inflammatory cells, fibroblasts, fibrocytes, collagen and the degree of vascularization. Stereological analysis inferred that porous scaffolds with regular topography are better tolerated in vivo compared to non-porous scaffolds, while increasing scaffold porosity promotes angiogenesis and cellular infiltration. The results suggest that this biodegradable polyesterurethane is better tolerated in vivo than the control and that structural variants of biodegradable polyesterurethane in vivo evoke a cellular and angiogenic response that is dictated by architecture.Irish Research Council for Science, Engineering and Technology: funded by the National Development Plan. Enterprise Ireland: Research Innovation Partnership

Performance and resource modeling for FPGAs using high-level synthesis tools

High-performance computing with FPGAs is gaining momentum with the advent of sophisticated High-Level Synthesis (HLS) tools. The performance of a design is impacted by the input-output bandwidth, the code optimizations and the resource consumption, making the performance estimation a challenge. This paper proposes a performance model which extends the roofline model to take into account the resource consumption and the parameters used in the HLS tools. A strategy is developed which maximizes the performance and the resource utilization within the area of the FPGA. The model is used to optimize the design exploration of a class of window-based image processing application

Bit-level pipelined digit-serial array processors

A new architecture for high performance digit-serial vector inner product (VIP) which can be pipelined to the bit-level is introduced. The design of the digit-serial vector inner product is based on a new systematic design methodology using radix-2n arithmetic. The proposed architecture allows a high level of bit-level pipelining to increase the throughput rate with minimum initial delay and minimum area. This will give designers greater flexibility in finding the best tradeoff between hardware cost and throughput rate. It is shown that sub-digit pipelined digit-serial structure can achieve a higher throughput rate with much less area consumption than an equivalent bit-parallel structure. A twin-pipe architecture to double the throughput rate of digit-serial multipliers and consequently that of the digit-serial vector inner product is also presented. The effect of the number of pipelining levels and the twin-pipe architecture on the throughput rate and hardware cost are discussed. A two's complement digit-serial architecture which can operate on both negative and positive numbers is also presented

Low power techniques for video compression

This paper gives an overview of low-power techniques proposed in the literature for mobile multimedia and Internet applications. Exploitable aspects are discussed in the behavior of different video compression tools. These power-efficient solutions are then classified by synthesis domain and level of abstraction. As this paper is meant to be a starting point for further research in the area, a lowpower hardware & software co-design methodology is outlined in the end as a possible scenario for video-codec-on-a-chip implementations on future mobile multimedia platforms