7 research outputs found

    Self-Clocked Shift Registers Utilizing 90 nm CMOS: Design, Analysis and Insights

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    This paper presents an efficient approach to designing and analyzing four bit shift register utilizing self-clocked D flip-flops as integral storage components. The use of internal clock generation within these flip-flops obviates the need for external clock synchronization. These specially designed flip-flops incorporate a reduced number of transistors in comparison to conventional designs, leading to notable enhancements in power efficiency, packaging density, and operational speed. The implementation of self-triggered D flip-flops facilitates the creation of various shift register configurations, including Serial in Serial out (SISO), Serial in Parallel out (SIPO), Parallel in Serial out (PISO), and Parallel in Parallel out (PIPO). These registers not only occupy a smaller die area but also exhibit diminished power consumption and heightened operational speed when contrasted with standard counterparts. The design and simulation procedures are executed using the Microwind tool and a 90 nm CMOS technology

    ๋ฉ”๋ชจ๋ฆฌ ์–ดํ”Œ๋ฆฌ์ผ€์ด์…˜์„ ์œ„ํ•œ ๋น ๋ฅธ ๊ณผ๋„ ์‘๋‹ต ์„ฑ๋Šฅ์„ ๊ฐ€์ง€๋Š” ๋””์ง€ํ„ธ ๋‚ฎ์€ ๋“œ๋กญ์•„์›ƒ ๋ ˆ๊ทค๋ ˆ์ดํ„ฐ ์„ค๊ณ„

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    ํ•™์œ„๋…ผ๋ฌธ(๋ฐ•์‚ฌ) -- ์„œ์šธ๋Œ€ํ•™๊ต๋Œ€ํ•™์› : ๊ณต๊ณผ๋Œ€ํ•™ ์ „๊ธฐยท์ •๋ณด๊ณตํ•™๋ถ€, 2023. 2. ์ •๋•๊ท .In this dissertation, the design of a fast transient response digital low-dropout regulator (DLDO) applicable to next-generation memory systems is discussed. Recent technologies in memory systems mainly aim at high power density and fast data rate. Accordingly, the need for a power converter withstanding a large amount of load current change in a short period is increased. Accordingly, a solution for compensating for a voltage drop that causes significant damage to a memory data input/output is searched according to a periodic clock signal. With this situation, two structures that achieve fast transient response performance under the constraints of memory systems are proposed. To mitigate the transient response degradation under slow external clock conditions, an adaptive two-step search algorithm with event-driven approaches DLDO is proposed. The technique solves the limitations of loop operation time dependent on slow external clocks through a ring-amplifier-based continuous-time comparator. Also, shift register is designed as a circular structure with centralized control of each register to reduce the cost. Finally, the remaining regulation error is controlled by an adaptive successive approximation algorithm to minimize the settling time. Fast recovery and settling time are shown through the measurement of the prototype chip implemented by the 40-nm CMOS process. Next, a digital low dropout regulator for ultra-fast transient response is designed. A slope-detector-based coarse controller to detect, compensate, and correct load current changes occurring at every rising or falling edge of tens to hundreds of megahertz clocks is proposed. Compensation efficiency is increased by the method according to the degree of change in load voltage over time. Furthermore, the LUT-based shift register enables the fast loop response speed of the DLDO. Finally, a bidirectional latch-based driver with fast settling speed and high resolution are proposed. The prototype chip is implemented with a 40-nm CMOS process and achieves effective load voltage recovery through fast transient response performance even with low load capacitance.๋ณธ ๋…ผ๋ฌธ์€ ์ฐจ์„ธ๋Œ€ ๋ฉ”๋ชจ๋ฆฌ ์‹œ์Šคํ…œ์— ์ ์šฉ ๊ฐ€๋Šฅํ•œ ๋น ๋ฅธ ๊ณผ๋„ ์‘๋‹ต ์„ฑ๋Šฅ์„ ๊ฐ€์ง€๋Š” ๋””์ง€ํƒˆ ๋‚ฎ์€ ๋“œ๋กญ์•„์›ƒ ๋ ˆ๊ทค๋ ˆ์ดํ„ฐ์˜ ์„ค๊ณ„์— ๋Œ€ํ•ด ๊ธฐ์ˆ ํ•œ๋‹ค. ๋ฉ”๋ชจ๋ฆฌ ์‹œ์Šคํ…œ์˜ ์ตœ๊ทผ ๊ธฐ์ˆ ๋“ค์€ ๋†’์€ ์ „๋ ฅ ๋ฐ€๋„์™€ ๋น ๋ฅธ ๋ฐ์ดํ„ฐ ์†๋„๋ฅผ ์ฃผ๋œ ๋ชฉํ‘œ๋กœ ํ•˜๋ฉฐ ์ด์— ๋งž์ถ”์–ด ๋‹จ๊ธฐ๊ฐ„, ๋งŽ์€ ์–‘์˜ ๋ถ€ํ•˜ ์ „๋ฅ˜ ๋ณ€ํ™”๋ฅผ ๊ฒฌ๋””๋Š” ํŒŒ์›Œ ์ปจ๋ฒ„ํ„ฐ์˜ ํ•„์š”์„ฑ์ด ๋†’์•„์ง€๊ณ  ์žˆ๋‹ค. ์ด์— ์ฃผ๊ธฐ์ ์ธ ํด๋ฝ ์‹ ํ˜ธ์— ๋”ฐ๋ผ ๋ฉ”๋ชจ๋ฆฌ ๋ฐ์ดํ„ฐ ์ž…์ถœ๋ ฅ์— ์œ ์˜๋ฏธํ•œ ์†์ƒ์„ ๋ฐœ์ƒ์‹œํ‚ค๋Š” ์ „์•• ๊ฐ•ํ•˜๋ฅผ ๋ณด์ƒํ•˜๋Š” ํ•ด๊ฒฐ ๋ฐฉ์•ˆ์„ ํƒ์ƒ‰ํ•œ๋‹ค. ์ด๋ฅผ ํ†ตํ•ด ๋ฉ”๋ชจ๋ฆฌ ์‹œ์Šคํ…œ์ด ๊ฐ€์ง€๋Š” ์ œ์•ฝ์กฐ๊ฑด ํ•˜์—์„œ ๋น ๋ฅธ ๊ณผ๋„ ์‘๋‹ต ์„ฑ๋Šฅ์„ ๋‹ฌ์„ฑํ•˜๋Š” ๋‘ ๊ฐ€์ง€ ๊ตฌ์กฐ๋ฅผ ์ œ์•ˆํ•œ๋‹ค. ์ฒซ ๋ฒˆ์งธ ์‹œ์—ฐ์œผ๋กœ์„œ, ๋Š๋ฆฐ ์™ธ๋ถ€ ํด๋ฝ ์กฐ๊ฑด์—์„œ ์œ ๋ฐœ๋˜๋Š” ๋””์ง€ํƒˆ ๋‚ฎ์€ ๋“œ๋กญ์•„์›ƒ ๋ ˆ๊ทค๋ ˆ์ดํ„ฐ์˜ ๊ณผ๋„ ์‘๋‹ต ์„ฑ๋Šฅ ์ €ํ•˜๋ฅผ ์™„ํ™”์‹œํ‚ค๊ธฐ ์œ„ํ•œ ์ด๋ฒคํŠธ ์ฃผ๋„ ๋ฐฉ์‹์˜ ์ ์‘ํ˜• ๋‘ ๋‹จ๊ณ„ ์„œ์น˜ ๊ธฐ์ˆ ์„ ์ œ์•ˆํ•œ๋‹ค. ๋ณธ ๊ธฐ์ˆ ์€ ๋Š๋ฆฐ ์™ธ๋ถ€ํด๋ฝ์— ์˜์กดํ•œ ๋ฃจํ”„ ๋™์ž‘ ์‹œ๊ฐ„์˜ ํ•œ๊ณ„๋ฅผ ๊ณ ๋ฆฌ ์ฆํญ๊ธฐ ๊ธฐ๋ฐ˜ ์—ฐ์† ์‹œ๊ฐ„ ๋น„๊ต๊ธฐ๋ฅผ ํ†ตํ•ด ํ•ด๊ฒฐํ•œ๋‹ค. ๋˜ํ•œ ์ž๋ฆฌ ์ด๋™ ๋ ˆ์ง€์Šคํ„ฐ์˜ ๊ตฌํ˜„์— ์†Œ๋ชจ๋˜๋Š” ๋น„์šฉ์„ ์ค„์ด๊ณ ์ž ๊ฐ ๋ ˆ์ง€์Šคํ„ฐ์˜ ์ œ์–ด ์žฅ์น˜๋ฅผ ์ค‘์•™์œผ๋กœ ์ง‘์ ์‹œํ‚จ ์ˆœํ™˜ํ˜• ๊ตฌ์กฐ๋กœ ์„ค๊ณ„๋˜์—ˆ๋‹ค. ๋งˆ์ง€๋ง‰์œผ๋กœ ๋‚จ์•„์žˆ๋Š” ์กฐ์ • ์—๋Ÿฌ๋Š” ์ ์‘๋ฐฉ์‹์˜ ์ถ•์ฐจ ๋น„๊ตํ˜• ์•Œ๊ณ ๋ฆฌ์ฆ˜์œผ๋กœ ์ œ์–ดํ•˜์—ฌ ๊ต์ •์— ํ•„์š”ํ•œ ์‹œ๊ฐ„์„ ์ตœ์†Œํ™”ํ•˜์˜€๋‹ค. 40-nm CMOS ๊ณต์ •์œผ๋กœ ๊ตฌํ˜„๋œ ํ”„๋กœํ† ํƒ€์ž… ์นฉ์˜ ์ธก์ •์„ ํ†ตํ•ด ๋ถ€ํ•˜ ์ „์••์˜ ๋น ๋ฅธ ํšŒ๋ณต ์†๋„์™€ ์ •์ •์‹œ๊ฐ„์„ ๋ณด์ž„์„ ํ™•์ธํ•˜์˜€๋‹ค. ๋‘ ๋ฒˆ์งธ ์‹œ์—ฐ์œผ๋กœ์„œ, ์ดˆ๊ณ ์† ๊ณผ๋„ ์‘๋‹ต ํ™˜๊ฒฝ์— ์ ํ•ฉํ•œ ๋””์ง€ํ„ธ ๋‚ฎ์€ ๋“œ๋กญ์•„์›ƒ ๋ ˆ๊ทค๋ ˆ์ดํ„ฐ๊ฐ€ ์„ค๊ณ„๋˜์—ˆ๋‹ค. ์ˆ˜์‹ญ~์ˆ˜๋ฐฑ ๋ฉ”๊ฐ€ํ—ค๋ฅด์ฏ” ํด๋ฝ์˜ ์ƒ์Šน ๋˜๋Š” ํ•˜๊ฐ• ์—ฃ์ง€๋งˆ๋‹ค ๋ฐœ์ƒํ•˜๋Š” ๋ถ€ํ•˜ ์ „๋ฅ˜ ๋ณ€ํ™”๋ฅผ ํƒ์ง€ํ•˜๊ณ  ๋ณด์ƒํ•˜๊ณ  ์ •์ •ํ•˜๊ธฐ ์œ„ํ•ด ๊ธฐ์šธ๊ธฐ ํƒ์ง€๊ธฐ ๊ธฐ๋ฐ˜ coarse ์ œ์–ด๊ธฐ ๊ธฐ์ˆ ์„ ์ œ์•ˆํ•œ๋‹ค. ์‹œ๊ฐ„์— ๋”ฐ๋ฅธ ๋ถ€ํ•˜ ์ „์•• ๋ณ€ํ™”์˜ ์ •๋„์— ๋”ฐ๋ผ ์ฐจ๋“ฑ ๋ณด์ƒํ•˜๋Š” ์•Œ๊ณ ๋ฆฌ์ฆ˜์„ ์ ์šฉํ•จ์œผ๋กœ์จ ๋ณด์ƒ ํšจ์œจ์„ ๋†’์˜€๋‹ค. ๋‚˜์•„๊ฐ€ ์ˆœ๋žŒํ‘œ ๊ธฐ๋ฐ˜ ์ž๋ฆฌ์ด๋™ ๋ ˆ์ง€์Šคํ„ฐ๋Š” ๋ถ€ํ•˜ ์ „๋ฅ˜ ๊ณผ๋„ ์ƒํƒœ ์ดํ›„ ๋””์ง€ํƒˆ ๋ ˆ๊ทค๋ ˆ์ดํ„ฐ์˜ ๋น ๋ฅธ ๋ฃจํ”„ ์‘๋‹ต ์†๋„๋ฅผ ๊ฐ€๋Šฅ์ผ€ ํ•˜์˜€๋‹ค. ๋งˆ์ง€๋ง‰์œผ๋กœ ๋‚จ์€ ์กฐ์ • ์—๋Ÿฌ๋ฅผ ์ œ์–ดํ•˜๋Š”๋ฐ ์žˆ์–ด์„œ ๊ธฐ์กด ์ž๋ฆฌ์ด๋™ ๋ ˆ์ง€์Šคํ„ฐ ๋ฐฉ์‹์—์„œ ๋ฒ—์–ด๋‚˜ ๋น ๋ฅธ ์ˆ˜๋ ด ์†๋„์™€ ๋†’์€ ํ•ด์ƒ๋„๋ฅผ ๊ฐ€์ง€๋Š” ์–‘๋ฐฉํ–ฅ ๋ž˜์น˜ ๊ธฐ๋ฐ˜ ๋“œ๋ผ์ด๋ฒ„๊ฐ€ ์ œ์•ˆ๋˜์—ˆ๋‹ค. ํ•ด๋‹น ํ”„๋กœํ† ํƒ€์ž… ์นฉ์€ 40-nm CMOS ๊ณต์ •์œผ๋กœ ๊ตฌํ˜„๋˜์—ˆ์œผ๋ฉฐ, ๋‚ฎ์€ ๋ถ€ํ•˜ ์ถ•์ „์šฉ๋Ÿ‰์—๋„ ๋น ๋ฅธ ๊ณผ๋„ ์‘๋‹ต ์„ฑ๋Šฅ์„ ํ†ตํ•ด ํšจ๊ณผ์ ์ธ ๋ถ€ํ•˜ ์ „์•• ํšŒ๋ณต์„ ์ด๋ฃจ์–ด ๋‚ด์—ˆ๋‹ค.CHAPTER 1 INTRODUCTION 1 1.1 MOTIVATION 1 1.2 VARIOUS TYPES OF LDO 4 1.2.1 ANALOG LDO VS. DIGITAL LDO 4 1.2.2 CAP LDO VS. CAP-LESS LDO 6 1.3 THESIS ORGANIZATION 8 CHAPTER 2 BACKGROUNDS ON DIGITAL LOW-DROPOUT REGULATOR 9 2.1 BASIC DIGITAL LOW-DROPOUT REGULATOR 9 2.2 FAST TRANSIENT RESPONSE LOW-DROPOUT REGULATOR 12 2.2.1 RESPONSE TIME 13 2.2.1 SETTLING TIME 20 2.3 VARIOUS METHODS FOR IMPLEMENT FAST TRANSIENT DIGITAL LDO 21 2.3.1 EVENT-DRIVEN DIGITAL LDO 21 2.3.2 FEEDFORWARD CONTROL 23 2.3.3 COMPUTATIONAL DIGITAL LDO 25 2.4 DESIGN POINTS OF FAST TRANSIENT RESPONSE DIGITAL LDO 27 CHAPTER 3 A FAST DROOP-RECOVERY EVENT-DRIVEN DIGITAL LDO WITH ADAPTIVE LINEAR/BINARY TWO-STEP SEARCH FOR VOLTAGE REGULATION IN ADVANCED MEMORY 29 3.1 OVERVIEW 29 3.2 PROPOSED DIGITAL LDO 32 3.2.1 MOTIVATION 32 3.2.2 ALSC WITH TWO-DIMENSIONAL CIRCULAR SHIFTING REGISTER 36 3.2.3 SBSC WITH SUBRANGE SUCCESSIVE-APPROXIMATION REGISTER 39 3.2.4 STABILITY ANALYSIS 41 3.3 CIRCUIT IMPLEMENTATION 44 3.3.1 TIME-INTERLEAVED RING-AMPLIFIER-BASED COMPARATOR 44 3.3.2 ASYNCHRONOUS 2D CIRCULAR SHIFTING REGISTER 49 3.3.3 SUBRANGE SUCCESSIVE APPROXIMATION REGISTER 51 3.4 MESUREMENT RESULTS 54 CHAPTER 4 A FAST TRANSIENT RESPONSE DIGITAL LOW-DROPOUT REGULATOR WITH SLOPE-DETECTOR-BASED MULTI-STEP CONTROL FOR DIGITAL LOAD APPLICATION 62 4.1 OVERVIEW 62 4.2 PROPOSED DIGITAL LDO 64 4.2.1 MOTIVATION 64 4.2.2 ARCHITECTURE OF DIGITAL LDO 66 4.2.3 SLEW-RATE DEPENDENT COARSE-CONTROL LOOP 69 4.2.4 FINE-CONTROL LOOP 72 4.2.5 CONTROL FOR LOAD-TRANSIENT RESPONSE 74 4.3 CIRCUIT IMPLEMENTATION 77 4.3.1 COMPARATOR-TRIGGERED OSCILLATOR DESIGN 77 4.3.2 SLOPE DETECTOR DESIGN 81 4.3.3 LUT-BASED SHIFT REGISTER DESIGN 84 4.3.4 BI-DIRECTIONAL LATCH-BASED DRIVER DESIGN 86 4.4 MEASUREMENT(SIMULATION) RESULTS 90 CHAPTER 5 CONCLUSION 95 BIBLIOGRAPHY 97 ์ดˆ ๋ก 109๋ฐ•

    Custom Integrated Circuit Design for Portable Ultrasound Scanners

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    A Case Study in CMOS Design Scaling for Analog Applications: The Ringamp LDO

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    As CMOS process nodes scale to smaller feature sizes, process optimizations are made to achieve improvements in digital circuit performance, such as increasing speed and memory, while decreasing power consumption. Unfortunately for analog design, these optimizations usually come at the expense of poorer transistor performance, such as reduced small signal output resistance and increased channel length modulation. The ring amplifier has been proposed as a digital solution to the analog scaling problem, by configuring digital inverters to function as analog amplifiers through deadzone biasing. As digital inverters naturally scale, the ring amplifier is a promising area of exploration for analog design. This work presents a ring amplifier scaling study by demonstration of scaling an output capacitor-less, ring amplifier based low-dropout voltage regulator designed in a standard 180 nm CMOS process down to a standard 90 nm CMOS process

    Modeling, Design and Optimization of IC Power Delivery with On-Chip Regulation

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    As IC technology continues to follow the Mooreโ€™s Law, IC designers have been constantly challenged with power delivery issues. While useful power must be reliably delivered to the on-die functional circuits to fulfill the desired functionality and performance, additional power overheads arise due to the loss associated with voltage conversion and parasitic resistance in the metal wires. Hence, one of the key IC power delivery design challenges is to develop voltage conversion/regulation circuits and the corresponding design strategies to provide a guaranteed level of power integrity while achieving high power efficiency and low area overhead. On-chip voltage regulation, a significant ongoing design trend, offers appealing active supply noise suppression close to the loads and is well positioned to address many power delivery challenges. However, to realize the full potential of on-chip voltage regulation requires systemic optimization of and tradeoffs among settling time, steady-state error, power supply noise, power efficiency, stability and area overhead, which are the key focuses of this dissertation. First, we develop new low-dropout voltage regulators (LDOs) that are well optimized for low power applications. To this end, dropout voltage, bias current and speed are important competing design objectives. This dissertation presents new flipped voltage follower (FVF) based topologies of on-chip voltage regulators that handle ultra-fast load transients in nanoseconds while achieving significant improvement on bias current consumption. An active frequency compensation is embedded to achieve high area efficiency by employing a smaller amount of compensation capacitors, the major silicon area contributor. Furthermore, in one of the proposed topologies an auxiliary digital feedback loop is employed in order to lower quiescent power consumption further. Second, coping with supply noise is becoming increasingly more difficult as design complexity grows, which leads to increased spatial and temporal load heterogeneity, and hence larger voltage variations in a given power domain. Addressing this challenge through a distributed methodology wherein multiple voltage regulators are placed across the same voltage domain is particularly promising. This distributive nature allows for even faster suppression of multiple hot spots by the nearby regulators within the power domain and can significantly boost power integrity. Nevertheless, reasoning about the stability of such distributively regulated power networks becomes rather complicated as a result of complex interactions between multiple active regulators and the large passive subnetwork. Coping with this stability challenge requires new theory and stability-ensuring design practice, as targeted by this dissertation. For the first time, we adopt and develop a hybrid stability framework for large power delivery networks with distributed voltage regulation. This framework is local in the sense that both the checking and assurance of network stability can be dealt with on the basis of each individual voltage regulator, leading to feasible design of large power delivery networks that would be computationally impossible otherwise. Accordingly, we propose a new hybrid stability margin concept, examine its tradeoffs with power efficiency, supply noise and silicon area, and demonstrate the resulted key design implications pertaining to new stability-ensuring LDO circuit design techniques and circuit topologies. Finally, we develop an automated hybrid stability design flow that is computationally efficient and provides a practical guarantee of network stability

    Integrated circuit & system design for concurrent amperometric and potentiometric wireless electrochemical sensing

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    Complementary Metal-Oxide-Semiconductor (CMOS) biosensor platforms have steadily grown in healthcare and commerial applications. This technology has shown potential in the field of commercial wearable technology, where CMOS sensors aid the development of miniaturised sensors for an improved cost of production and response time. The possibility of utilising wireless power and data transmission techniques for CMOS also allows for the monolithic integration of the communication, power and sensing onto a single chip, which greatly simplifies the post-processing and improves the efficiency of data collection. The ability to concurrently utilise potentiometry and amperometry as an electrochemical technique is explored in this thesis. Potentiometry and amperometry are two of the most common transduction mechanisms for electrochemistry, with their own advantages and disadvantages. Concurrently applying both techniques will allow for real-time calibration of background pH and for improved accuracy of readings. To date, developing circuits for concurrently sensing potentiometry and amperometry has not been explored in the literature. This thesis investigates the possibility of utilising CMOS sensors for wireless potentiometric and amperometric electrochemical sensing. To start with, a review of potentiometry and amperometry is evaluated to understand the key factors behind their operation. A new configuration is proposed whereby the reference electrode for both electrochemistry techniques are shared. This configuration is then compared to both the original configurations to determine any differences in the sensing accuracy through a novel experiment that utilises hydrogen peroxide as a measurement analyte. The feasibility of the configuration with the shared reference electrode is proven and utilised as the basis of the electrochemical configuration for the front end circuits. A unique front-end circuit named DAPPER is developed for the shared reference electrode topology. A review of existing architectures for potentiometry and amperometry is evaluated, with a specific focus on low power consumption for wireless applications. In addition, both the electrochemical sensing outputs are mixed into a single output data channel for use with a near-field communication (NFC). This mixing technique is also further analysed in this thesis to understand the errors arising due to various factors. The system is fabricated on TSMC 180nm technology and consumes 28ยตW. It measures a linear input current range from 250pA - 0.1ยตW, and an input voltage range of 0.4V - 1V. This circuit is tested and verified for both electrical and electrochemical tests to showcase its feasibility for concurrent measurements. This thesis then provides the integration of wireless blocks into the system for wireless powering and data transmission. This is done through the design of a circuit named SPACEMAN that consists of the concurrent sensing front-end, wireless power blocks, data transmission, as well as a state machine that allows for the circuit to switch between modes: potentiometry only, amperometry only, concurrent sensing and none. The states are switched through re-booting the circuit. The core size of the electronics is 0.41mmยฒ without the coil. The circuitโ€™s wireless powering and data transmission is tested and verified through the use of an external transmitter and a connected printed circuit board (PCB) coil. Finally, the future direction for ongoing work to proceed towards a fully monolithic electrochemical technique is discussed through the next development of a fully integrated coil-on-CMOS system, on-chip electrodes with the electroplating and microfludics, the development of an external transmitter for powering the device and a test platform. The contributions of this thesis aim to formulate a use for wireless electrochemical sensors capable of concurrent measurements for use in wearable devices.Open Acces
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