Self-Clocked Shift Registers Utilizing 90 nm CMOS: Design, Analysis and Insights

This paper presents an efficient approach to designing and analyzing four bit shift register utilizing self-clocked D flip-flops as integral storage components. The use of internal clock generation within these flip-flops obviates the need for external clock synchronization. These specially designed flip-flops incorporate a reduced number of transistors in comparison to conventional designs, leading to notable enhancements in power efficiency, packaging density, and operational speed. The implementation of self-triggered D flip-flops facilitates the creation of various shift register configurations, including Serial in Serial out (SISO), Serial in Parallel out (SIPO), Parallel in Serial out (PISO), and Parallel in Parallel out (PIPO). These registers not only occupy a smaller die area but also exhibit diminished power consumption and heightened operational speed when contrasted with standard counterparts. The design and simulation procedures are executed using the Microwind tool and a 90 nm CMOS technology

메모리 어플리케이션을 위한 빠른 과도 응답 성능을 가지는 디지털 낮은 드롭아웃 레귤레이터 설계

학위논문(박사) -- 서울대학교대학원 : 공과대학 전기·정보공학부, 2023. 2. 정덕균.In this dissertation, the design of a fast transient response digital low-dropout regulator (DLDO) applicable to next-generation memory systems is discussed. Recent technologies in memory systems mainly aim at high power density and fast data rate. Accordingly, the need for a power converter withstanding a large amount of load current change in a short period is increased. Accordingly, a solution for compensating for a voltage drop that causes significant damage to a memory data input/output is searched according to a periodic clock signal. With this situation, two structures that achieve fast transient response performance under the constraints of memory systems are proposed. To mitigate the transient response degradation under slow external clock conditions, an adaptive two-step search algorithm with event-driven approaches DLDO is proposed. The technique solves the limitations of loop operation time dependent on slow external clocks through a ring-amplifier-based continuous-time comparator. Also, shift register is designed as a circular structure with centralized control of each register to reduce the cost. Finally, the remaining regulation error is controlled by an adaptive successive approximation algorithm to minimize the settling time. Fast recovery and settling time are shown through the measurement of the prototype chip implemented by the 40-nm CMOS process. Next, a digital low dropout regulator for ultra-fast transient response is designed. A slope-detector-based coarse controller to detect, compensate, and correct load current changes occurring at every rising or falling edge of tens to hundreds of megahertz clocks is proposed. Compensation efficiency is increased by the method according to the degree of change in load voltage over time. Furthermore, the LUT-based shift register enables the fast loop response speed of the DLDO. Finally, a bidirectional latch-based driver with fast settling speed and high resolution are proposed. The prototype chip is implemented with a 40-nm CMOS process and achieves effective load voltage recovery through fast transient response performance even with low load capacitance.본 논문은 차세대 메모리 시스템에 적용 가능한 빠른 과도 응답 성능을 가지는 디지탈 낮은 드롭아웃 레귤레이터의 설계에 대해 기술한다. 메모리 시스템의 최근 기술들은 높은 전력 밀도와 빠른 데이터 속도를 주된 목표로 하며 이에 맞추어 단기간, 많은 양의 부하 전류 변화를 견디는 파워 컨버터의 필요성이 높아지고 있다. 이에 주기적인 클락 신호에 따라 메모리 데이터 입출력에 유의미한 손상을 발생시키는 전압 강하를 보상하는 해결 방안을 탐색한다. 이를 통해 메모리 시스템이 가지는 제약조건 하에서 빠른 과도 응답 성능을 달성하는 두 가지 구조를 제안한다. 첫 번째 시연으로서, 느린 외부 클락 조건에서 유발되는 디지탈 낮은 드롭아웃 레귤레이터의 과도 응답 성능 저하를 완화시키기 위한 이벤트 주도 방식의 적응형 두 단계 서치 기술을 제안한다. 본 기술은 느린 외부클락에 의존한 루프 동작 시간의 한계를 고리 증폭기 기반 연속 시간 비교기를 통해 해결한다. 또한 자리 이동 레지스터의 구현에 소모되는 비용을 줄이고자 각 레지스터의 제어 장치를 중앙으로 집적시킨 순환형 구조로 설계되었다. 마지막으로 남아있는 조정 에러는 적응방식의 축차 비교형 알고리즘으로 제어하여 교정에 필요한 시간을 최소화하였다. 40-nm CMOS 공정으로 구현된 프로토타입 칩의 측정을 통해 부하 전압의 빠른 회복 속도와 정정시간을 보임을 확인하였다. 두 번째 시연으로서, 초고속 과도 응답 환경에 적합한 디지털 낮은 드롭아웃 레귤레이터가 설계되었다. 수십~수백 메가헤르쯔 클락의 상승 또는 하강 엣지마다 발생하는 부하 전류 변화를 탐지하고 보상하고 정정하기 위해 기울기 탐지기 기반 coarse 제어기 기술을 제안한다. 시간에 따른 부하 전압 변화의 정도에 따라 차등 보상하는 알고리즘을 적용함으로써 보상 효율을 높였다. 나아가 순람표 기반 자리이동 레지스터는 부하 전류 과도 상태 이후 디지탈 레귤레이터의 빠른 루프 응답 속도를 가능케 하였다. 마지막으로 남은 조정 에러를 제어하는데 있어서 기존 자리이동 레지스터 방식에서 벗어나 빠른 수렴 속도와 높은 해상도를 가지는 양방향 래치 기반 드라이버가 제안되었다. 해당 프로토타입 칩은 40-nm CMOS 공정으로 구현되었으며, 낮은 부하 축전용량에도 빠른 과도 응답 성능을 통해 효과적인 부하 전압 회복을 이루어 내었다.CHAPTER 1 INTRODUCTION 1 1.1 MOTIVATION 1 1.2 VARIOUS TYPES OF LDO 4 1.2.1 ANALOG LDO VS. DIGITAL LDO 4 1.2.2 CAP LDO VS. CAP-LESS LDO 6 1.3 THESIS ORGANIZATION 8 CHAPTER 2 BACKGROUNDS ON DIGITAL LOW-DROPOUT REGULATOR 9 2.1 BASIC DIGITAL LOW-DROPOUT REGULATOR 9 2.2 FAST TRANSIENT RESPONSE LOW-DROPOUT REGULATOR 12 2.2.1 RESPONSE TIME 13 2.2.1 SETTLING TIME 20 2.3 VARIOUS METHODS FOR IMPLEMENT FAST TRANSIENT DIGITAL LDO 21 2.3.1 EVENT-DRIVEN DIGITAL LDO 21 2.3.2 FEEDFORWARD CONTROL 23 2.3.3 COMPUTATIONAL DIGITAL LDO 25 2.4 DESIGN POINTS OF FAST TRANSIENT RESPONSE DIGITAL LDO 27 CHAPTER 3 A FAST DROOP-RECOVERY EVENT-DRIVEN DIGITAL LDO WITH ADAPTIVE LINEAR/BINARY TWO-STEP SEARCH FOR VOLTAGE REGULATION IN ADVANCED MEMORY 29 3.1 OVERVIEW 29 3.2 PROPOSED DIGITAL LDO 32 3.2.1 MOTIVATION 32 3.2.2 ALSC WITH TWO-DIMENSIONAL CIRCULAR SHIFTING REGISTER 36 3.2.3 SBSC WITH SUBRANGE SUCCESSIVE-APPROXIMATION REGISTER 39 3.2.4 STABILITY ANALYSIS 41 3.3 CIRCUIT IMPLEMENTATION 44 3.3.1 TIME-INTERLEAVED RING-AMPLIFIER-BASED COMPARATOR 44 3.3.2 ASYNCHRONOUS 2D CIRCULAR SHIFTING REGISTER 49 3.3.3 SUBRANGE SUCCESSIVE APPROXIMATION REGISTER 51 3.4 MESUREMENT RESULTS 54 CHAPTER 4 A FAST TRANSIENT RESPONSE DIGITAL LOW-DROPOUT REGULATOR WITH SLOPE-DETECTOR-BASED MULTI-STEP CONTROL FOR DIGITAL LOAD APPLICATION 62 4.1 OVERVIEW 62 4.2 PROPOSED DIGITAL LDO 64 4.2.1 MOTIVATION 64 4.2.2 ARCHITECTURE OF DIGITAL LDO 66 4.2.3 SLEW-RATE DEPENDENT COARSE-CONTROL LOOP 69 4.2.4 FINE-CONTROL LOOP 72 4.2.5 CONTROL FOR LOAD-TRANSIENT RESPONSE 74 4.3 CIRCUIT IMPLEMENTATION 77 4.3.1 COMPARATOR-TRIGGERED OSCILLATOR DESIGN 77 4.3.2 SLOPE DETECTOR DESIGN 81 4.3.3 LUT-BASED SHIFT REGISTER DESIGN 84 4.3.4 BI-DIRECTIONAL LATCH-BASED DRIVER DESIGN 86 4.4 MEASUREMENT(SIMULATION) RESULTS 90 CHAPTER 5 CONCLUSION 95 BIBLIOGRAPHY 97 초 록 109박

A Case Study in CMOS Design Scaling for Analog Applications: The Ringamp LDO

As CMOS process nodes scale to smaller feature sizes, process optimizations are made to achieve improvements in digital circuit performance, such as increasing speed and memory, while decreasing power consumption. Unfortunately for analog design, these optimizations usually come at the expense of poorer transistor performance, such as reduced small signal output resistance and increased channel length modulation. The ring amplifier has been proposed as a digital solution to the analog scaling problem, by configuring digital inverters to function as analog amplifiers through deadzone biasing. As digital inverters naturally scale, the ring amplifier is a promising area of exploration for analog design. This work presents a ring amplifier scaling study by demonstration of scaling an output capacitor-less, ring amplifier based low-dropout voltage regulator designed in a standard 180 nm CMOS process down to a standard 90 nm CMOS process

Modeling, Design and Optimization of IC Power Delivery with On-Chip Regulation

As IC technology continues to follow the Moore’s Law, IC designers have been constantly challenged with power delivery issues. While useful power must be reliably delivered to the on-die functional circuits to fulfill the desired functionality and performance, additional power overheads arise due to the loss associated with voltage conversion and parasitic resistance in the metal wires. Hence, one of the key IC power delivery design challenges is to develop voltage conversion/regulation circuits and the corresponding design strategies to provide a guaranteed level of power integrity while achieving high power efficiency and low area overhead. On-chip voltage regulation, a significant ongoing design trend, offers appealing active supply noise suppression close to the loads and is well positioned to address many power delivery challenges. However, to realize the full potential of on-chip voltage regulation requires systemic optimization of and tradeoffs among settling time, steady-state error, power supply noise, power efficiency, stability and area overhead, which are the key focuses of this dissertation. First, we develop new low-dropout voltage regulators (LDOs) that are well optimized for low power applications. To this end, dropout voltage, bias current and speed are important competing design objectives. This dissertation presents new flipped voltage follower (FVF) based topologies of on-chip voltage regulators that handle ultra-fast load transients in nanoseconds while achieving significant improvement on bias current consumption. An active frequency compensation is embedded to achieve high area efficiency by employing a smaller amount of compensation capacitors, the major silicon area contributor. Furthermore, in one of the proposed topologies an auxiliary digital feedback loop is employed in order to lower quiescent power consumption further. Second, coping with supply noise is becoming increasingly more difficult as design complexity grows, which leads to increased spatial and temporal load heterogeneity, and hence larger voltage variations in a given power domain. Addressing this challenge through a distributed methodology wherein multiple voltage regulators are placed across the same voltage domain is particularly promising. This distributive nature allows for even faster suppression of multiple hot spots by the nearby regulators within the power domain and can significantly boost power integrity. Nevertheless, reasoning about the stability of such distributively regulated power networks becomes rather complicated as a result of complex interactions between multiple active regulators and the large passive subnetwork. Coping with this stability challenge requires new theory and stability-ensuring design practice, as targeted by this dissertation. For the first time, we adopt and develop a hybrid stability framework for large power delivery networks with distributed voltage regulation. This framework is local in the sense that both the checking and assurance of network stability can be dealt with on the basis of each individual voltage regulator, leading to feasible design of large power delivery networks that would be computationally impossible otherwise. Accordingly, we propose a new hybrid stability margin concept, examine its tradeoffs with power efficiency, supply noise and silicon area, and demonstrate the resulted key design implications pertaining to new stability-ensuring LDO circuit design techniques and circuit topologies. Finally, we develop an automated hybrid stability design flow that is computationally efficient and provides a practical guarantee of network stability

Voltage and Time-Domain Analog Circuit Techniques for Scaled CMOS Technologies

CMOS technology scaling has resulted in reduced supply voltage and intrinsic voltage gain of the transistor. This presents challenges to the analog circuit designers due to lower signal swing and achievable signal to noise ratio (SNR), leading to increased power consumption. At the same time, device speed has increased in lower design nodes, which has not been directly beneficial for analog circuit design. This thesis presents voltage-domain and time-domain circuit scaling friendly circuit architectures that minimize the power consumption and benefit from the increasing transistor speeds. In the voltage-domain, an on-the-fly gain selection block is demonstrated as an alternative to the traditional MDAC architecture to enhance the input dynamic range of a medium-resolution medium-speed analog-to-digital converter (ADC) at reduced supply voltages. The proposed design also eliminates the need for a reference buffer, thus providing power savings. The measured prototype enhances the input dynamic range of a 12bit, 40MSPS ADC to 80.6dB at 1.2V supply voltage. In the time-domain, a generic circuit design approach is presented, followed by an in-depth analysis of Voltage-Controlled-Oscillator based Operational Transconductance Amplifiers (VCO-OTAs). A discrete-time-domain small-signal model based on the zero crossings of the internal VCOs is developed to predict the stability, the step response, and the frequency response of the circuit when placed in feedback. The model accurately predicts the circuit behavior for an arbitrary input frequency, even as the VCO free-running frequency approaches the unity-gain bandwidth of the closed-loop system, where other intuitive small-signal models available in the literature fail. Next, we present an application of VCO-OTA in designing a baseband trans-impedance amplifier (TIA) for current-mode receivers as a scaling-friendly and power-efficient alternative to the inverter-based OTA. We illustrate a design methodology for the choice of the VCO-OTA parameters in the context of a receiver design with an example of a 20MHz RF-channel-bandwidth receiver operating at 2GHz. Receiver simulation results demonstrate an improvement of up to 12dB in blocker 1dB compression point (B1dB) for slightly higher power consumption or up to 2.6x power reduction of the TIA resulting in up to 2x power reduction of the receiver for similar B1dB performance. Next, we present some examples of VCO-OTAs. We first illustrate the benefit of a VCO-OTA in a low-dropout-voltage regulator to achieve a dropout voltage of only100mV and operating down to 0.8V input supply, compared to the prototype based on traditional OTA with a minimum dropout voltage of 150mV, operating at a minimum of 1.2V supply. Both the capacitor-less prototypes can drive up to 1nF load capacitor and provide a current of 60mA. The next prototype showcases a method to reduce the power consumption of a VCO-OTA and spurs at the VCO frequency, with an application in the design of a fourth-order Butterworth filter at 4MHz. The thesis concludes with a design example of 0.2V VCO-OTA

Integrated circuit & system design for concurrent amperometric and potentiometric wireless electrochemical sensing

Complementary Metal-Oxide-Semiconductor (CMOS) biosensor platforms have steadily grown in healthcare and commerial applications. This technology has shown potential in the field of commercial wearable technology, where CMOS sensors aid the development of miniaturised sensors for an improved cost of production and response time. The possibility of utilising wireless power and data transmission techniques for CMOS also allows for the monolithic integration of the communication, power and sensing onto a single chip, which greatly simplifies the post-processing and improves the efficiency of data collection. The ability to concurrently utilise potentiometry and amperometry as an electrochemical technique is explored in this thesis. Potentiometry and amperometry are two of the most common transduction mechanisms for electrochemistry, with their own advantages and disadvantages. Concurrently applying both techniques will allow for real-time calibration of background pH and for improved accuracy of readings. To date, developing circuits for concurrently sensing potentiometry and amperometry has not been explored in the literature. This thesis investigates the possibility of utilising CMOS sensors for wireless potentiometric and amperometric electrochemical sensing. To start with, a review of potentiometry and amperometry is evaluated to understand the key factors behind their operation. A new configuration is proposed whereby the reference electrode for both electrochemistry techniques are shared. This configuration is then compared to both the original configurations to determine any differences in the sensing accuracy through a novel experiment that utilises hydrogen peroxide as a measurement analyte. The feasibility of the configuration with the shared reference electrode is proven and utilised as the basis of the electrochemical configuration for the front end circuits. A unique front-end circuit named DAPPER is developed for the shared reference electrode topology. A review of existing architectures for potentiometry and amperometry is evaluated, with a specific focus on low power consumption for wireless applications. In addition, both the electrochemical sensing outputs are mixed into a single output data channel for use with a near-field communication (NFC). This mixing technique is also further analysed in this thesis to understand the errors arising due to various factors. The system is fabricated on TSMC 180nm technology and consumes 28µW. It measures a linear input current range from 250pA - 0.1µW, and an input voltage range of 0.4V - 1V. This circuit is tested and verified for both electrical and electrochemical tests to showcase its feasibility for concurrent measurements. This thesis then provides the integration of wireless blocks into the system for wireless powering and data transmission. This is done through the design of a circuit named SPACEMAN that consists of the concurrent sensing front-end, wireless power blocks, data transmission, as well as a state machine that allows for the circuit to switch between modes: potentiometry only, amperometry only, concurrent sensing and none. The states are switched through re-booting the circuit. The core size of the electronics is 0.41mm² without the coil. The circuit’s wireless powering and data transmission is tested and verified through the use of an external transmitter and a connected printed circuit board (PCB) coil. Finally, the future direction for ongoing work to proceed towards a fully monolithic electrochemical technique is discussed through the next development of a fully integrated coil-on-CMOS system, on-chip electrodes with the electroplating and microfludics, the development of an external transmitter for powering the device and a test platform. The contributions of this thesis aim to formulate a use for wireless electrochemical sensors capable of concurrent measurements for use in wearable devices.Open Acces