Experimental and simulation study of 1D silicon nanowire transistors using heavily doped channels

The experimental results from 8 nm diameter silicon nanowire junctionless field effect transistors with gate lengths of 150 nm are presented that demonstrate on-currents up to 1.15 mA/m for 1.0 V and 2.52 mA/m for 1.8 V gate overdrive with an off-current set at 100 nA/m. On- to off-current ratios above 108 with a subthreshold slope of 66 mV/dec are demonstrated at 25 oC. Simulations using drift-diffusion which include densitygradient quantum corrections provide excellent agreement with the experimental results. The simulations demonstrate that the present silicon-dioxide gate dielectric only allows the gate to be scaled to 25 nm length before short-channel effects significantly reduce the performance. If high-K dielectrics replace some parts of the silicon dioxide then the technology can be scaled to at least 10 nm gatelength

Generation of tunable, high repetition rate optical frequency combs using on-chip silicon modulators

We experimentally demonstrate tunable, highly-stable frequency combs with high repetition-rates using a single, charge injection based silicon PN modulator. In this work, we demonstrate combs in the C-band with over 8 lines in a 20-dB bandwidth. We demonstrate continuous tuning of the center frequency in the C-band and tuning of the repetition-rate from 7.5GHz to 12.5GHz. We also demonstrate through simulations the potential for bandwidth scaling using an optimized silicon PIN modulator. We find that, the time varying free carrier absorption due to carrier injection, an undesirable effect in data modulators, assists here in enhancing flatness in the generated combs.Comment: 10 pages, 7 figure

Electric field control of confined magnetic skyrmions for energy efficient scalable nanomagnetic memory

Nanomagnetic random-access-memory (RAM) devices are considered one of the leading alternatives to the existing Complementary Metal Oxide Semiconductor (CMOS) based RAM devices due to inherent non-volatility and long endurance compared to other non-CMOS devices. However, new paradigms such as voltage control and spin orbit torque are being explored to write information with low errors in an energy efficient manner. Magnetic skyrmions have emerged as potentially viable paradigm for nanomagnetic memory devices because of their robustness, scalability and extremely low energy requirement for creation and manipulation. Besides, electric field induced manipulation of nanomagnets as well as magnetic skyrmions has been shown to be a promising strategy towards the implementation of ultra-low power memory devices. One such electric field-based manipulation of magnetic states involves skyrmion mediated switching of perpendicular magnetic tunnel junctions (p-MTJs) based nanomagnetic memory devices. This is achieved by applying a voltage pulse starting from a ferromagnetic up/down state to reduce PMA, thus creating an intermediate skyrmion and subsequently annihilating the skyrmion by withdrawing the voltage pulse to achieve ferromagnetic down/up (i.e. reversed) state. However, scalability of skyrmions confined in a nanodot and skyrmion-mediated voltage-controlled switching strategy have not been completely investigated, particularly their scaling to 20 nm lateral dimension and beyond. In this study, we investigated the feasibility of scaling of perpendicular MTJs to lateral dimensions ~20nm and beyond, as well as dynamic skyrmion-mediated switching in such MTJs in the presence of room temperature thermal noise and defects/edge roughness

Development of room temperature operating single electron transistor using FIB etching and deposition technology

The single-electron transistor (SET) is one of the best candidates for future nano electronic circuits because of its ultralow power consumption, small size and unique functionality. SET devices operate on the principle of Coulomb blockade, which is more prominent at dimensions of a few nano meters. Typically, the SET device consists of two capacitively coupled ultra-small tunnel junctions with a nano island between them. In order to observe the Coulomb blockade effects in a SET device the charging energy of the device has to be greater that the thermal energy. This condition limits the operation of most of the existing SET devices to cryogenic temperatures. Room temperature operation of SET devices requires sub-10nm nano-islands due to the inverse dependence of charging energy on the radius of the conducting nano-island. Fabrication of sub-10nm structures using lithography processes is still a technological challenge. In the present investigation, Focused Ion Beam based etch and deposition technology is used to fabricate single electron transistors devices operating at room temperature. The SET device incorporates an array of tungsten nano-islands with an average diameter of 8nm. The fabricated devices are characterized at room temperature and clear Coulomb blockade and Coulomb oscillations are observed. An improvement in the resolution limitation of the FIB etching process is demonstrated by optimizing the thickness of the active layer. SET devices with structural and topological variation are developed to explore their impact on the behavior of the device. The threshold voltage of the device was minimized to ~500mV by minimizing the source-drain gap of the device to 17nm. Vertical source and drain terminals are fabricated to realize single-dot based SET device. A unique process flow is developed to fabricate Si dot based SET devices for better gate controllability in the device characteristic. The device vi parameters of the fabricated devices are extracted by using a conductance model. Finally, characteristic of these devices are validated with the simulated data from theoretical modeling

A CMOS-Compatible Poly-Si Nanowire Device with Hybrid Sensor/Memory Characteristics for System-on-Chip Applications

This paper reports a versatile nano-sensor technology using “top-down” poly-silicon nanowire field-effect transistors (FETs) in the conventional Complementary Metal-Oxide Semiconductor (CMOS)-compatible semiconductor process. The nanowire manufacturing technique reduced nanowire width scaling to 50 nm without use of extra lithography equipment, and exhibited superior device uniformity. These n type polysilicon nanowire FETs have positive pH sensitivity (100 mV/pH) and sensitive deoxyribonucleic acid (DNA) detection ability (100 pM) at normal system operation voltages. Specially designed oxide-nitride-oxide buried oxide nanowire realizes an electrically Vth-adjustable sensor to compensate device variation. These nanowire FETs also enable non-volatile memory application for a large and steady Vth adjustment window (>2 V Programming/Erasing window). The CMOS-compatible manufacturing technique of polysilicon nanowire FETs offers a possible solution for commercial System-on-Chip biosensor application, which enables portable physiology monitoring and in situ recording

Physical IC debug ─ backside approach and nanoscale challenge

Physical analysis for IC functionality in submicron technologies requires access through chip backside. Based upon typical global backside preparation with 50–100 µm moderate silicon thickness remaining, a state of the art of the analysis techniques available for this purpose is presented and evaluated for functional analysis and layout pattern resolution potential. A circuit edit technique valid for nano technology ICs, is also presented that is based upon the formation of local trenches using the bottom of Shallow Trench Isolation (STI) as endpoint for Focused Ion Beam (FIB) milling. As a derivative from this process, a locally ultra thin silicon device can be processed, creating a back surface as work bench for breakthrough applications of nanoscale analysis techniques to a fully functional circuit through chip backside. Several applications demonstrate the power and potential of this new approach