A robust high-efficiency cross-coupled charge pump circuit without blocking transistors

This document is the Accepted Manuscript version of the following article: Minglin Ma, Xinglong Cai, Yichuang Sun, and Nike George, ‘A robust high-efficiency cross-coupled charge pump circuit without blocking transistors’, Analog Integrated Circuits and Signal Processing, Vol. 95 (3): 395-401, June 2018. Under embargo until 16 March 2019. The final publication is available at Springer via: https://doi.org/10.1007/s10470-018-1149-xA fully integrated cross-coupled charge pump circuit with a new clock scheme has been presented in this paper. The new clock scheme ensures that all NMOS pre-charge transistors are turned off when the voltages of main clock signals are high. Notably, all PMOS transfer transistors will be turned off when the voltages of the main clock signals are low. As a result, the charge pump eliminates all of the reversion power loss and reduces the ripple voltage. The proposed charge pump has a better performance even in scenarios where the main clock signals are mismatched. The proposed charge pump circuit was simulated using spectre in the TSMC 0.18 µm CMOS process. The simulation results show that the proposed charge pump circuit has a high voltage conversion efficiency and low ripple voltage.Peer reviewe

A Charge Pump Architecture with High Power-Efficiency and Low Output Ripple Noise in 0.5 μm CMOS Process Technology

The demand of portable consumer electronic devices is skyrocketing day-by-day. Such modern integrated microsystems have several functional blocks which require different voltages to operate adequately. DC-DC converter circuits are used to generate different voltage domains for different functional blocks on large integrated microsystems from a single voltage battery-operated power supply. Charge pump is an inductorless DC-DC converter which generates higher positive voltage or lower voltage or negative voltage from the applied reference voltage. A charge pump circuit uses switches for charge transfer action and capacitors for charge storage. The thesis presents a high power-efficiency charge pump architecture with low output ripple noise in the AMI N-well 0.5 µm CMOS process technology. The switching action of the proposed charge pump architecture is controlled by a dual phase non-overlapping clock system. In order to achieve high power-efficiency, the power losses due to the leakage currents, the finite switch resistance and the imperfect charge transfer between the capacitors are taken into consideration and are minimized by proper switching of the charge transfer switches and by using different auxiliary circuits. To achieve low output ripple noise, the continuous current pumping method is proposed and implemented in the charge pump architecture. The proposed charge pump can operate over the wide input voltage range varying from 3 V to 7 V with the power conversion efficiency of 90%. The loading current drive capability of the proposed charge pump is ranging from 0 to 45 mA. The worst case output ripple voltage is less than 25 mV. To prove the concept, the design of the proposed charge pump is simulated rigorously over different process, temperature and voltage corners

High-efficiency high voltage hybrid charge pump design with an improved chip area

A hybrid charge pump was developed in a 0.13- $\mu \text{m}$ Bipolar-CMOS-DMOS (BCD) process which utilised high drain-source voltage MOS devices and low-voltage integrated metal-insulator-metal (MIM) capacitors. The design consisted of a zero-reversion loss cross-coupled stage and a new self-biased serial-parallel charge pump design. The latter has been shown to have an area reduction of 60% in comparison to a Schottky diode-based Dickson charge pump operating at the same frequency. Post-layout simulations were carried out which demonstrated a peak efficiency of 38% at the output voltage of 18.5 V; the maximum specified output voltage of 27 V was also achieved. A standalone serial-parallel charge pump was shown to have a better transient response and a flatter efficiency curve; these are preferable for time-sensitive applications with a requirement of a broader range of output currents. These findings have significant implications for reducing the total area of implantable high-voltage devices without sacrificing charge pump efficiency or maximum output voltage

Analysis and design of switched-capacitor DC-DC converters with discrete event models

Ph. D. Thesis.Switched-capacitor DC-DC converters (SCDDCs) play a critical role in low power integrated systems. The analysis and design processes of an SCDDC impact the performance and power efficiency of the whole system. Conventionally, researchers carry out the analysis and design processes by viewing SCDDCs as analogue circuits. Analogue attributes of an SCDDC, such as the charge flow current or the equivalent output impedance, have been studied in considerable detail for performance enhancement. However, in most existing work, less attention is paid to the analysis of discrete events (e.g. digital signal transitions) and the relationships between discrete events in SCDDCs. These discrete events and the relationships between discrete events also affect the performance of SCDDCs. Certain negative effects of SCDDCs such as leakage current are introduced by unhealthy discrete states. For example, MOS devices in an SCDDC could conduct undesirably under certain combinations of signals, resulting in reversion losses (a type of leakage in SCDDCs). However, existing work only use verbal reasoning and waveform descriptions when studying these discrete events, which may cause confusion and result in an informal design process consisting of intuitive design and backed up merely by validation based on natural language discussions and simulations. There is therefore a need for formalised methods to describe and analyse these discrete events which may facilitate systematic design techniques. This thesis presents a new method of analysing and designing SCDDCs using discrete event models. Discrete event models such as Petri nets and Signal Transition Graphs (STGs) are commonly used in asynchronous circuits to formally describe and analyse the relationships between discrete transitions. Modelling SCDDCs with discrete event models provides a formal way to describe the relations between discrete transitions in SCDDCs. These discrete event models can be used for analysis, verification and even design guidance for SCDDC design. The rich set of existing analysis methods and tools for discrete event models could be applied to SCDDCs, potentially improving the analysis and design flow for them. Moreover, since Petri nets and STGs are generally used to analyse and design asynchronous circuits, modelling and designing SCDDCs with STG models may additionally facilitate the incorporation of positive features of asynchronous circuits in SCDDCs (e.g. no clock skew). In this thesis, the relations between discrete events in SCDDCs are formally described with SC-STG (an extended STG targeting multi-voltage systems, to which SCDDCs belong), which avoids the potential confusion due to natural language and waveform descriptions. Then the concurrency and causality relations described in SC-STG model are extended to Petri nets, with which the presence of reversion losses can be formally determined and verified. Finally, based on the STG and Petri net models, a new design method for reversion-loss-free SCDDCs is proposed. In SCDDCs designed with the new method, reversion losses are entirely removed by introducing asynchronous controls, synthesised with the help of a software synthesis toolkit “Workcraft”. To demonstrate the analysis capabilities of the method, several cross-coupled voltage doublers (a type of SCDDC) are analysed and studied with discrete event models as examples in this thesis. To demonstrate the design capabilities of the method, a new reversion-loss-free cross-coupled voltage doubler is designed. The cross-coupled voltage doubler is widely used in low power integrated systems such as flash memories, LCD drivers and wireless energy harvesting systems. The proposed modelling method is potentially used in both research and industrial area of those applications for a formal and high-efficiency design proces

Design of a Quasi-Adiabatic Current-Mode Neurostimulator Integrated Circuit for Deep Brain Stimulation

Electrical stimulation of neural tissues is a valuable tool in the retinal prosthesis, cardiac pacemakers, and Deep Brain Stimulation (DBS). DBS is being to treat a growing number of neurological disorders, such as movement disorder, epilepsy, and Parkinson’s disease. The role of the electronic stimulator is paramount in such application, and significant design challenges are to be met to enhance safety and reliability. A current-source based stimulator can accurately deliver a charge-balanced stimulus maintaining patient safety. In this thesis, a general-purpose current-mode neurostimulator (CMS) based upon a new quasi-adiabatic driving technique is proposed which can theoretically achieve more than 80% efficiency with the help of a dynamic high voltage supply (DHVS) as opposed to most conventional general-purpose CMS having less than 25% efficiency. The high-voltage supply is required to withstand the voltage seen across the electrodes (>10V) due to the time-varying impedance presented by the electrode-tissue interface. The overall efficiency of the designed CMS is limited by the efficiency of the DHVS. A HVDD of 15V is created by the DHVS from an input voltage (VDD) of 3V. The DHVS circuit is made by cascading five charge pump circuits using the AMI 0.5µm CMOS process. It can maintain more than 60% efficiency for a wide range of load current from 25µA to 1.4mA, with peak efficiency at 67% and this is comparable with existing specific-purpose state-of-the-art high-voltage supplies used in a current stimulator. The stimulator designed in this thesis employs a new efficient charge recycling mechanism to enhance the overall efficiency, compared to the existing state-of-the-art CMSs. Thus, the overall CMS efficiency is improved by 20% to 25%. A current source, programmable by 8-bit digital input, is also designed which has an output impedance greater than 2MΩ with a dropout voltage of only 120mV. Measurements show voltage compliance exceeding +/-15V when driving a biphasic current stimulus of 10µA to 2.5mA through a simplified R-C model of the electrode-tissue interface. The voltage compliance is defined as the maximum voltage a stimulator can apply across the electrodes to achieve neural stimulation

Power management systems based on switched-capacitor DC-DC converter for low-power wearable applications

The highly efficient ultra-low-power management unit is essential in powering low-power wearable electronics. Such devices are powered by a single input source, either by a battery or with the help of a renewable energy source. Thus, there is a demand for an energy conversion unit, in this case, a DC-DC converter, which can perform either step-up or step-down conversions to provide the required voltage at the load. Energy scavenging with a boost converter is an intriguing choice since it removes the necessity of bulky batteries and considerably extends the battery life. Wearable devices are typically powered by a monolithic battery. The commonly available battery such as Alkaline or Lithium-ion, degrade over time due to their life spans as it is limited by the number of charge cycles- which depend highly on the environmental and loading condition. Thus, once it reaches the maximum number of life cycles, the battery needs to be replaced. The operation of the wearable devices is limited by usable duration, which depends on the energy density of the battery. Once the stored energy is depleted, the operation of wearable devices is also affected, and hence it needs to be recharged. The energy harvesters- which gather the available energy from the surroundings, however, have no limitation on operating life. The application can become battery-less given that harvestable energy is sufficiently powering the low-power devices. Although the energy harvester may not completely replace the battery source, it ensures the maximum duration of use and assists to become autonomous and self-sustain devices. The photovoltaic (PV) cell is a promising candidate as a hypothetical input supply source among the energy harvesters due to its smaller area and high power density over other harvesters. Solar energy use PV harvester can convert ambient light energy into electrical energy and keep it in the storage device. The harvested output of PV cannot directly connect to wearable loads for two main reasons. Depending on the incoming light, the harvested current result in varying open-circuit voltage. It requires the power management circuit to deal with unregulated input variation. Second, depending on the PV cell's material type and an effective area, the I-V characteristic's performance varies, resulting in a variation of the output power. There are several works of maximum power point tracking (MPPT) methods that allow the solar energy harvester to achieve optimal harvested power. Therefore, the harvested power depends on the size and usually small area cell is sufficient for micro-watt loads low-powered applications. The available harvested voltage, however, is generally very low-voltage range between 0.4-0.6 V. The voltage ratings of electronics in standard wearable applications operate in 1.8-3 V voltages as described in introduction’s application example section. It is higher than the supply source can offer. The overcome the mismatch voltage between source and supply circuit, a DC-DC boost converter is necessary. The switch-mode converters are favoured over the linear converters due to their highly efficient and small area overhead. The inductive converter in the switch-mode converter is common due to its high-efficiency performance. However, the integration of the inductor in the miniaturised integrated on-chip design tends to be bulky. Therefore, the switched-capacitor approach DC-DC converters will be explored in this research. In the switched-capacitor converter universe, there is plenty of work for single-output designs for various topologies. Most converters are reconfigurable to the different DC voltage levels apart from Dickson and cross-coupled charge pump topologies due to their boosting power stage architecture through a number of stages. However, existing multi-output converters are limited to the fixed gain ratio. This work explores the reconfigurable dual-output converter with adjustable gain to compromise the research gap. The thesis's primary focus is to present the inductor-less, switched-capacitor-based DC-DC converter power management system (PMS) supplied by a varying input of PV energy harvester input source. The PMS should deliver highly efficient regulated voltage conversion ratio (VCR) outputs to low-power wearable electronic devices that constitute multi-function building blocks

MEMS piezoelectric vibrational energy harvesters and circuits for IoT applications

In the Internet of Things (IoT) world, more and more sensor nodes are being deployed and more mobile power sources are required. Alternative solutions to batteries are the subjects of worldwide extended research. Among the possibilities is the harvesting of energy from the ambient. A novel energy harvesting system to power wireless sensor nodes is a necessity and inevitable path, with more and more market interest. Microelectromechnaical systems (MEMS) based piezoelectric vibrational energy harvesters (PVEH) are considered in this thesis due to their good energy densities, conversion efficiency, suitability for miniaturization and CMOS integration. Cantilever beams are favored for their relatively high average strains, low frequencies and simplicity of fabrication. Proof masses are essential in micro scale devices in order to decrease the resonance frequency and increase the strain along the beam to increase the output power. In this thesis, the effects of proof mass geometry on piezoelectric vibration energy harvesters are studied. Different geometrical dimension ratios have significant impact on the resonance frequency, e.g., beam to mass lengths, and beam to mass widths. The responses of various prototypes are studied. Furthermore, the impact of geometry on the performance of cantilever-based PVEH is investigated. Namely, rectangular and trapezoidal T-shaped designs are fabricated and tested. Optimized cross-shaped geometries are fabricated using a commercial technology PiezoMUMPs process from MEMSCAP. They are characterized for their resonant frequency, strain distribution and output power. The output of an energy harvester is not directly suited as a power supply for circuits because of variations in its power and voltage over time, therefore a power management circuit is required. The circuit meets the requirements of responding to an input voltage that varies with the ambient conditions to generate a regulated output voltage, and the ability to power multiple outputs from a fixed input voltage. In this thesis, new design architectures for a reconfigurable circuit are considered. A charge pump which modifies dynamically the number of stages to generate a plurality of voltage levels has been designed and fabricated using a CMOS 0.13 μm technology. This provides biasing voltages for electrostatic MEMS devices. Electrostatic MEMS require relatively high and variable actuation voltages and the fabricated circuit serves this goal and attains a measured maximum output voltage of 10.1 V from a 1.2 V supply. In this thesis, design recommendations are given and MEMS piezoelectric harvesters are implemented and validated through fabrications. T-shaped harvesters bring improvements over cantilever designs, namely the trapezoidal T-shaped structures. A cross-shaped design has the advantage of utilizing four beams and the proposed proof mass improves the performance significantly. A cross-coupled circuit rectifies the output efficiently towards an optimal energy harvesting solution

Novel charge pump architecture with Fibonacci stage

U ovoj je doktorskoj disertaciji predstavljena nova arhitektura nabojske pumpe. U prvom dijelu rada opisan je osnovni princip rada najčešće korištene nabojske pumpe, Dicksonove nabojske pumpe, te razvijen njen novi matematički model. Novi matematički model je primjenjiv na bilo koju dvo faznu nabojsku pumpu i od postojećih se razlikuje po tome što uzima u obzir utjecaj otpora kanala tranzistora i izvora. Na osnovu predstavljenog matematičkog modela, predložena je nova metoda za određivanje parametara nabojske pumpe, koja također uzima u obzir otpor kanala tranzistora i otpor izvora, te je generalizirana tako da odgovara bilo kojoj dvo faznoj nabojskoj pumpi. Nabojske pumpe visokog dobitka, koje su u posljednje vrijeme postale popularne, također se mogu opisati predstavljenim matematičkim modelom i predloženom metodom određivanja parametara, ako koriste dva protufazna signala takta. Nakon teorijskih i matematičkih analiza, koje uključuju i utjecaj efekta podloge na napon praga tranzistora, predložena je nova arhitektura nabojske pumpe s Fibonaccijevim stupnjem. Proces projektiranja integriranog CMOS sklopa u Cadence okruženju je detaljno opisan i prikazani su rezultati simulacije sa i bez ekstrahiranih paratiznih parametara. Korištenjem Fibonaccijevom stupnja dobiveni su viši izlazni naponi od izlaznih napona klasičnih arhitektura nabojskih pumpi, a CVSL sklop je dokazan kao jednostavno i efikasno rješenje za ispravno upravljanje Fibonaccijevim stupnjem. Nova arhitektura nabojske pumpe je procesirana u sklopu testnog integriranog sklopa korištenjem 0,35 μm AMS-ovog C35B4C3 tehnološkog procesa, zajedno s Dicksonovom, CTS i modificiranom CTS nabojskom pumpom koje služe za usporedbu s novom arhitekturom. Rezultati mjerenja su uspoređeni s rezultatima simulacije, a njihova međusobna odstupanja su detaljno objašnjena. Na temelju usporedbe mjernih i simulacijskih rezultata, dokazano je da SPICE model netočno modelira rad tranzistora u području ispon napona praga te time i ponašanje nabojske pumpe za čisto kapacitivna opterećenja. Također, utvrđeno je formiranje niskopropusnog filtra na priključcima signala takta kod testnog integriranog sklopa, te su predložene metode za rješavanje tog problema.In this doctoral thesis a novel charge pump architecture is presented. In the first part of the thesis the basic principles of operation of the most common charge pump, Dickson charge pump, are described and a novel mathematical model is developed and presented. The presented model is appliable to any two-phase charge pump and it takes into account resistance of MOSFET switches and the power supply resistance as well. Based on the presented mathematical model, a new method for charge pump parameter determination is proposed, which also takes into account the switch and the power supply resistance, and it is generalized to correspond to any two-phase charge pump. Recent high gain charge pump designs, as long as they are two-phase designs, can also be descibed with presented mathematical model and proposed method. After theoretical and mathematical analysis, including body effect on the threshold voltage of the NMOS devices, a novel charge pump architecture with Fibonacci stage is presented. Designing process in Cadence environment is explained in detail and simulation results, both with and without exctracted parasitics, are given. The higher output voltages of the novel architecture, compared with common charge pump architectures, due to used Fibonacci stage are observed and the CVSL circuit is proven to be simple and efficient solution for high amplitude clock generator that is needed to drive the Fibonacci stage. The novel charge pump is proccessed in integrated circuit using 0,35 µm AMS C35B4C3 technology process, together with Dickson, CTS and modified CTS charge pump which are used for comparison with new architecture. Measurements of the fabricated charge pumps are compared with simulation results and the discrepancies are explained. Based on the measurement and simulation comparison, the SPICE model behavior in subthreshold region for a charge pump operating under capacitive load is proved to be faulty. Also, the forming of the low-pass filter on the clock signal pins in processed and bonded integrated circuit is determined, and some solutions are proposed

Dichotomic role of NAADP/two-pore channel 2/Ca2+ signaling in regulating neural differentiation of mouse embryonic stem cells

Poster Presentation - Stem Cells and Pluripotency: abstract no. 1866The mobilization of intracellular Ca2+stores is involved in diverse cellular functions, including cell proliferation and differentiation. At least three endogenous Ca2+mobilizing messengers have been identified, including inositol trisphosphate (IP3), cyclic adenosine diphosphoribose (cADPR), and nicotinic adenine acid dinucleotide phosphate (NAADP). Similar to IP3, NAADP can mobilize calcium release in a wide variety of cell types and species, from plants to animals. Moreover, it has been previously shown that NAADP but not IP3-mediated Ca2+increases can potently induce neuronal differentiation in PC12 cells. Recently, two pore channels (TPCs) have been identified as a novel family of NAADP-gated calcium release channels in endolysosome. Therefore, it is of great interest to examine the role of TPC2 in the neural differentiation of mouse ES cells. We found that the expression of TPC2 is markedly decreased during the initial ES cell entry into neural progenitors, and the levels of TPC2 gradually rebound during the late stages of neurogenesis. Correspondingly, perturbing the NAADP signaling by TPC2 knockdown accelerates mouse ES cell differentiation into neural progenitors but inhibits these neural progenitors from committing to the final neural lineage. Interestingly, TPC2 knockdown has no effect on the differentiation of astrocytes and oligodendrocytes of mouse ES cells. Overexpression of TPC2, on the other hand, inhibits mouse ES cell from entering the neural lineage. Taken together, our data indicate that the NAADP/TPC2-mediated Ca2+signaling pathway plays a temporal and dichotomic role in modulating the neural lineage entry of ES cells; in that NAADP signaling antagonizes ES cell entry to early neural progenitors, but promotes late neural differentiation.postprin