Memory built-in self-repair and correction for improving yield: a review

Nanometer memories are highly prone to defects due to dense structure, necessitating memory built-in self-repair as a must-have feature to improve yield. Today’s system-on-chips contain memories occupying an area as high as 90% of the chip area. Shrinking technology uses stricter design rules for memories, making them more prone to manufacturing defects. Further, using 3D-stacked memories makes the system vulnerable to newer defects such as those coming from through-silicon-vias (TSV) and micro bumps. The increased memory size is also resulting in an increase in soft errors during system operation. Multiple memory repair techniques based on redundancy and correction codes have been presented to recover from such defects and prevent system failures. This paper reviews recently published memory repair methodologies, including various built-in self-repair (BISR) architectures, repair analysis algorithms, in-system repair, and soft repair handling using error correcting codes (ECC). It provides a classification of these techniques based on method and usage. Finally, it reviews evaluation methods used to determine the effectiveness of the repair algorithms. The paper aims to present a survey of these methodologies and prepare a platform for developing repair methods for upcoming-generation memories

Особливості вбудованого самотестування і самовідновлення мікросхем пам'яті

Стаття присвячена питанням підвищення коефіцієнта технічної готовності мікросхем пам'яті. запропоновано архітектура вбудованих засобів само тестування та відновлення, що дозволяє виконати заміну розряду даних основного масиву запам'ятовуючих осередків, в якому стався відмову, на дані, що надходять з виходів запасного масиву запам'ятовуючих осередків. Запропоновані апаратні засоби забезпечують автоматичну реконфігурацію даних мікросхеми при виявленні відмови.Статья посвящена вопросам повышения коэффициента технической готовности микросхем памяти. предложено архитектура встроенных средств само тестирование и восстановление, что позволяет выполнить замену разряда данных основного массива запоминающих ячеек, в котором произошел отказ, на данные, поступающие с выходов запасного массива запоминающих ячеек. Предлагаемые аппаратные средства обеспечивают автоматическую реконфигурацию данных микросхемы при обнаружении отказа.Article is devoted to increasing the coefficient of technical readiness of memory chips. Рroposed architecture built-in self test and recovery, allowing for replacement of the discharge data of the main array storage cells in which there was a failure, the data coming from the outputs of the spare array storage cells. The proposed hardware provides automatic reconfiguration of data circuits in the detection of rejection

Design and Implementation of Repair-aware Test Flow for Multi-Memory

ABSTRAC

An Integrated Built-in Test and Repair Approach for Memories with 2D Redundancy

An efficient on-chip infrastructure for memory test and repair is crucial to enhance yield and availability of SoCs. Therefore embedded memories are commonly equipped with spare rows and columns (2D redundancy). To avoid the storage of large failure bitmaps needed by classical algorithms for offline repair analysis, existing heuristics for built-in repair analysis (BIRA) either follow very simple search strategies or restrict the search to smaller local bitmaps. Exact BIRA algorithms work with sub analyzers for each possible repair combination. While a parallel implementation suffers from a high hardware overhead, a serial implementation leads to high test times. The integrated built-in test and repair approach proposed in this paper interleaves test and repair analysis and supports an exact solution without failure bitmap. The basic search procedure is combined with an efficient technique to continuously reduce the problem complexity and keep the test and analysis time low. 1

Analyzing Test and Repair Times for 2D Integrated Memory Built-in Test and Repair

An efficient on-chip infrastructure for memory test and repair is crucial to enhance yield and availability of SoCs. A commonly used repair strategy is to equip memories with spare rows and columns (2D redundancy). To avoid the prohibitive storage requirements for failure bitmaps and the complex data structures inherent in most algorithms for offline repair analysis, existing heuristics for built-in repair analysis (BIRA) either use very simple search strategies or restrict the search to smaller local bitmaps. Exact BIRA algorithms work with sub analyzers for each possible repair combination. While a parallel implementation suffers from a high hardware overhead, a serial implementation leads to increased test times. Recently an integrated builtin test and repair approach has been proposed which interleaves test and repair analysis and supports an exact solution with moderate hardware overhead and reasonable test times. The search is based on a depth first traversal of a binary tree, which can be efficiently implemented using a stack of limited size. This algorithm can be realized with different repair strategies guiding the selection of spare rows or columns in each step. In this paper the impact of four different repair strategies on the test and repair time is analyzed