Transition Faults and Transition Path Delay Faults: Test Generation, Path Selection, and Built-In Generation of Functional Broadside Tests

As the clock frequency and complexity of digital integrated circuits increase rapidly, delay testing is indispensable to guarantee the correct timing behavior of the circuits. In this dissertation, we describe methods developed for three aspects of delay testing in scan-based circuits: test generation, path selection and built-in test generation. We first describe a deterministic broadside test generation procedure for a path delay fault model named the transition path delay fault model, which captures both large and small delay defects. Under this fault model, a path delay fault is detected only if all the individual transition faults along the path are detected by the same test. To reduce the complexity of test generation, sub-procedures with low complexity are applied before a complete branch-and-bound procedure. Next, we describe a method based on static timing analysis to select critical paths for test generation. Logic conditions that are necessary for detecting a path delay fault are considered to refine the accuracy of static timing analysis, using input necessary assignments. Input necessary assignments are input values that must be assigned to detect a fault. The method calculates more accurate path delays, selects paths that are critical during test application, and identifies undetectable path delay faults. These two methods are applicable to off-line test generation. For large circuits with high complexity and frequency, built-in test generation is a cost-effective method for delay testing. For a circuit that is embedded in a larger design, we developed a method for built-in generation of functional broadside tests to avoid excessive power dissipation during test application and the overtesting of delay faults, taking the functional constraints on the primary input sequences of the circuit into consideration. Functional broadside tests are scan-based two-pattern tests for delay faults that create functional operation conditions during test application. To avoid the potential fault coverage loss due to the exclusive use of functional broadside tests, we also developed an optional DFT method based on state holding to improve fault coverage. High delay fault coverage can be achieved by the developed method for benchmark circuits using simple hardware

Test Pattern Generation Using LFSR with Reseeding Scheme for BIST Designs

ABSTRACT: In this paper we present LFSR reseeding scheme for BIST. A time -to -market efficient algorithm is introduced for selecting reseeding points in the test sequence. This algorithm targets complete fault coverage and minimization of the test length. Functional broadside tests that avoid over testing by ensuring that a circuit traverses only reachable states during the functional clock cycles of a tes

On-Chip Generation of Functional Tests with Reduced Delay and Power

This paper describes different methods on-chip test generation method for functional tests. The hardware was based on application of primary input sequences in order to allow the circuit to produce reachable states. Random primary input sequences were modeled to avoid repeated synchronization and thus yields varied sets of reachable states by implementing a decoder in between circuit and LFSR. The on-chip generation of functional tests require simple hardware and achieved high transition fault coverage for testable circuits. Further, power and delay can be reduced by using Bit Swapping LFSR (BS-LFSR). This technique yields less number of transitions for all pattern generation. Bit-swapping (BS) technique is less complex and more reliable to hardware miscommunications

On-chip Generation of Functional Tests with Reduced Delay and Power

This paper describes different methods  on-chip test generation method for functional tests. The hardware was based on application of primary input sequences in order to allow the circuit to produce reachable states. Random primary input sequences were modeled to avoid repeated synchronization and thus yields varied sets of reachable states by implementing a decoder in between circuit and LFSR. The on-chip generation of functional tests require simple hardware and achieved high transition fault coverage for testable circuits. Further, power and delay can be reduced by using Bit Swapping LFSR (BS-LFSR). This technique yields less number of transitions for all pattern generation. Bit-swapping (BS) technique is less complex and more reliable to hardware miscommunications

Compressed Skewed-Load Delay Test Generation Based on Evolution and Deterministic Initialization of Populations

The current design and manufacturing semiconductor technologies require to test the products against delay related defects. However, complex acpSOC require low-overhead testability methods to keep the test cost at an acceptable level. Skewed-load tests seem to be the appropriate way to test delay faults in these acpSOC because the test application requires only one storage element per scan cell. Compressed skewed-load test generator based on genetic algorithm is proposed for wrapper-based logic cores of acpSOC. Deterministic population initialization is used to ensure the highest achievable aclTDF coverage for the given wrapper and scan cell order. The developed method performs test data compression by generating test vectors containing already overlapped test vector pairs. The experimental results show high fault coverages, decreased test lengths and better scalability in comparison to recent methods

Multi-Cycle Test with Partial Observation on Scan-Based BIST Structure

Field test for reliability is usually performed with small amount of memory resource, and it requires a new technique which might be somewhat different from the conventional manufacturing tests. This paper proposes a novel technique that improves fault coverage or reduces the number of test vectors that is needed for achieving the given fault coverage on scan-based BIST structure. We evaluate a multi-cycle test method that observes the values of partial flip-flops on a chip during capture-mode. The experimental result shows that the partial observation achieves fault coverage improvement with small hardware overhead than the full observation.2011 Asian Test Symposium (ATS), 20-23 Nov. 2011, New Delhi, Indi

Engineering evaluations and studies. Volume 2: Exhibit B, part 1

Ku-band communication system analysis, S-band system investigations, payload communication investigations, shuttle/TDRSS and GSTDN compatibility analysis are discussed

Millimeter-Wave Beam-Formed Array Antenna for Connected Driving Scenarios

Connected vehicles are the next frontier in massive mobile communications. The automotive industry is pursuing the exchange of essential information between vehicles, road infrastructure and all kind of external agents (V2X) for improving safety and traffic efficiency. Sharing data such as the position or kinematics, for example, can be used by other road participants to make a better prediction of hazardous situations. Even though, to meet the automotive-grade requirements, such as reliability during information exchange, or to support highly-automated applications such as platooning, high levels of reliability during information exchange are required. These cannot be sustained by the sub-6 GHz V2X band so it is therefore necessary to relocate to other bands such as the millimeter- Wave (mmWave) Frequency Range 2 (FR2) band, where larger bandwidths are available. The goal of this project is to develop a mmWave beam-formed array antenna for connected driving scenarios. With this framework, it will be possible to obtain metrics and understand how channel measurements can be used to improve V2X communications, by using for instance, di?erent antenna setups or combining di?erent beamforming strategies i.e. beam steering or beam shaping in diverse down-scaled urban scenarios. Based on this, it is largely intended to use physical layer measurements as a promising first barrier to improve the quality of V2X communications. MmWave communications for advanced connected and automated vehicle driving scenarios have drawn significant attention for their adaptability in a wide variety of applications. However, when Line-Of-Sight (LOS) and link stability cannot be assured in urban scenarios, the exchange of information between two vehicles becomes more complex and sometimes even dangerous if the information sent through the channel is not reliable. In this thesis, an improved mmWave beamforming method based on array antenna beam steering is presented. By using a channel-aware imaging algorithm, it aims to solve in large part the above-mentioned problematic by finding the most reliable path in non Line-Of- Sight (NLOS) scenarios. Thus, link stability over road infrastructures might be potentially improved besides enhancing safe-channel communications and traffic efficiency