Further Specialization of Clustered VLIW Processors: A MAP Decoder for Software Defined Radio

Turbo codes are extensively used in current communications standards and have a promising outlook for future generations. The advantages of software defined radio, especially dynamic reconfiguration, make it very attractive in this multi-standard scenario. However, the complex and power consuming implementation of the maximum a posteriori (MAP) algorithm, employed by turbo decoders, sets hurdles to this goal. This work introduces an ASIP architecture for the MAP algorithm, based on a dual-clustered VLIW processor. It displays the good performance of application specific designs along with the versatility of processors, which makes it compliant with leading edge standards. The machine deals with multi-operand instructions in an innovative way, the fetching and assertion of data is serialized and the addressing is automatized and transparent for the programmer. The performance-area trade-off of the proposed architecture achieves a throughput of 8 cycles per symbol with very low power dissipation

A COMMUNICATION FRAMEWORK FOR MULTIHOP WIRELESS ACCESS AND SENSOR NETWORKS: ANYCAST ROUTING & SIMULATION TOOLS

The reliance on wireless networks has grown tremendously within a number of varied application domains, prompting an evolution towards the use of heterogeneous multihop network architectures. We propose and analyze two communication frameworks for such networks. A first framework is designed for communications within multihop wireless access networks. The framework supports dynamic algorithms for locating access points using anycast routing with multiple metrics and balancing network load. The evaluation shows significant performance improvement over traditional solutions. A second framework is designed for communication within sensor networks and includes lightweight versions of our algorithms to fit the limitations of sensor networks. Analysis shows that this stripped down version can work almost equally well if tailored to the needs of a sensor network. We have also developed an extensive simulation environment using NS-2 to test realistic situations for the evaluations of our work. Our tools support analysis of realistic scenarios including the spreading of a forest fire within an area, and can easily be ported to other simulation software. Lastly, we us our algorithms and simulation environment to investigate sink movements optimization within sensor networks. Based on these results, we propose strategies, to be addressed in follow-on work, for building topology maps and finding optimal data collection points. Altogether, the communication framework and realistic simulation tools provide a complete communication and evaluation solution for access and sensor networks

Feasibility study of multiantenna transmitter baseband processing on customized processor core in wireless local area devices

The world of wireless communications is governed by a wide variety of the standards, each tailored to its specific applications and targets. The IEEE802.11 family is one of those standards which is specifically created and maintained by IEEE committee to im-plement the Wireless Local Area Network (WLAN) communication. By notably rapid growth of devices which exploit the WLAN technology and increasing demand for rich multimedia functionalities and broad Internet access, the WLAN technology should be necessarily enhanced to support the required specifications. In this regard, IEEE802.11ac, the latest amendment of the WLAN technology, was released which is taking advantage of the previous draft versions while benefiting from certain changes especially to the PHY layer to satisfy the promised requirements. This thesis evaluates the feasibility of software-based implementation for the MIMO transmitter baseband processing conforming to the IEEE802.11ac standard on a DSP core with vector extensions. The transmitter is implemented in four different transmis-sion scenarios which include 2x2 and 4x4 MIMO configurations, yielding beyond 1Gbps transmit bit rate. The implementation is done for the frequency-domain pro-cessing and real-time operation has been achieved when running at a clock fre-quency of 500MHz. The developed software solution is evaluated by profiling and analysing the imple-mentation using the tools provided by the vendor. We have presented the results with regards to number of clock cycles, power and energy consumption, and memory usage. The performance analysis shows that the SDR based implementation provides improved flexibility and reduced design effort compared to conventional approaches while main-taining power consumption close to fixed-function hardware solutions