Looking towards the future: the changing nature of intrusive surveillance and technical attacks against high-profile targets

In this thesis a novel Bayesian model is developed that is capable of predicting the probability of a range of eavesdropping techniques deployed, given an attacker's capability, opportunity and intent. Whilst limited attention by academia has focused on the cold war activities of Soviet bloc and Western allies' bugging of embassies, even less attention has been paid to the changing nature of the technology used for these eavesdropping events. This thesis makes four contributions: through the analysis of technical eavesdropping events over the last century, technological innovation is shown to have enriched the eavesdropping opportunities for a range of capabilities. The entry barrier for effective eavesdropping is lowered, while for the well resourced eavesdropper, the requirement for close access has been replaced by remote access opportunities. A new way to consider eavesdropping methods is presented through the expert elicitation of capability and opportunity requirements for a range of present-day eavesdropping techniques. Eavesdropping technology is shown to have life-cycle stages with the technology exploited by different capabilities at different times. Three case studies illustrate that yesterday’s secretive government method becomes today’s commodity. The significance of the egress transmission path is considered too. Finally, by using the expert elicitation information derived for capability, opportunity and life-cycle position, for a range of eavesdropping techniques, it is shown that it is possible to predict the probability of particular eavesdropping techniques being deployed. This novel Bayesian inferencing model enables scenarios with incomplete, uncertain or missing detail to be considered. The model is validated against the previously collated historic eavesdropping events. The development of this concept may be scaled with additional eavesdropping techniques to form the basis of a tool for security professionals or risk managers wishing to define eavesdropping threat advice or create eavesdropping policies based on the rigour of this technological study.Open Acces

uRT51: An Embedded Real-Time processor implemented on FPGA devices

In this paper we describe and evaluate the main features of the uRT51 processor. The uRT51 processor was designed for embedded realtime control applications. It is a processor architecture that incorporates the specific functions of a real-time system in hardware. It was described using synthesizable VHDL and it was implemented on FPGA devices. We describe how the uRT51 processor supports time, events, task and priorities. The performance of the uRT51 processor is evaluated using a control application as a case study. The experiments show that the uRT51 processor scheduling features outperform the ones obtained using a traditional RTOS-based real-time system.Fil: Cayssials, Ricardo Luis. Consejo Nacional de Investigaciones Científicas y Técnicas. Centro Científico Tecnológico Conicet - Bahía Blanca; Argentina. Universidad Nacional del Sur. Departamento de Ingeniería Eléctrica y de Computadoras; ArgentinaFil: Duval, M,. Provincia de Buenos Aires. Gobernación. Comisión de Investigaciones Científicas; Argentina. Universidad Nacional del Sur. Departamento de Ingeniería Eléctrica y de Computadoras; ArgentinaFil: Ferro, Edgardo Carlos. Universidad Nacional del Sur. Departamento de Ingeniería Eléctrica y de Computadoras; Argentina. Consejo Nacional de Investigaciones Científicas y Técnicas. Centro Científico Tecnológico Conicet - Bahía Blanca; ArgentinaFil: Alimenti, O.. Consejo Nacional de Investigaciones Científicas y Técnicas. Centro Científico Tecnológico Conicet - Bahía Blanca; Argentina. Universidad Nacional del Sur. Departamento de Ingeniería Eléctrica y de Computadoras; Argentin

THE IMPLICATIONS OF INTERNET ON THE MEDIA AND THE PRACTICE OF MASS COMMUNICATION

Internet has emerged as a communication medium and its impact on society, commerce and the government is already phenomenal. As the nerve centre of the new media technologies, it has revolutionized the whole business of mass communication. This paper therefore examines the media convergence that the Internet has created and its revolution of the nature of mass communication. It also explores the various dimensions by which the digital revolution has affected all aspects ofmediaprofession, fromproduction, distribution, storage and use of media content, to the practice of media profession

Testing Java ME Applications

Today, mobile applications have a wide use and their development is growing fast. Testing mobile applications is an important aspect of their development, keeping in mind the importance of these applications and their specific characteristics. In this paper are shown the main aspects of testing the mobile applications, focusing on unit testing of Java ME applications.mobile applications, mobile devices, software testing, WAP, Java ME, Junit

De-Bugging Open Source Software Licensing

Home computer users and businesses often rely on software developed by unconventional programmers known as hackers. Hackers claim that the code they develop is superior in quality to the code developed by commercial software firms because hackers freely share the code they develop. This code sharing enables a multitude of programmers from around the world to rapidly find and fix bugs. The legal mechanism that enables hackers to deploy this worldwide team of de-buggers is a license agreement or, to be more precise,an assortment of license agreements known as open source licenses. Although open source software developers may regularly fix buggy software, they do not regularly fix their licenses. There are a multitude of licenses that purport to meet the goals of open source development. These licenses reflect different, and sometimes contradictory, approaches to core licensing issues. Many of these licenses are buggy-out of date, misapplied, misunderstood and hopelessly confusing. This state of affairs benefits no one. Hackers suffer because they do not know which license form to use. End users suffer because they do not fully understand the terms of use. Commercial software developers suffer because they have difficulty discerning how open source licensed software may affect their intellectual property. The key to successfully de-bugging open source licensing is setting up a better process for creating and updating open source licenses. This article outlines one such process. This article begins by describing the array of open source licenses. It then explains the significant shortcomings in these licenses.The article concludes by proposing that a standards organization assume responsibility for improving important open source license forms and licensing practices

SpinLink: An interconnection system for the SpiNNaker biologically inspired multi-computer

SpiNNaker is a large-scale biologically-inspired multi-computer designed to model very heavily distributed problems, with the flagship application being the simulation of large neural networks. The project goal is to have one million processors included in a single machine, which consequently span many thousands of circuit boards. A computer of this scale imposes large communication requirements between these boards, and requires an extensible method of connecting to external equipment such as sensors, actuators and visualisation systems. This paper describes two systems that can address each of these problems.Firstly, SpinLink is a proposed method of connecting the SpiNNaker boards by using time-division multiplexing (TDM) to allow eight SpiNNaker links to run at maximum bandwidth between two boards. SpinLink will be deployed on Spartan-6 FPGAs and uses a locally generated clock that can be paused while the asynchronous links from SpiNNaker are sending data, thus ensuring a fast and glitch-free response. Secondly, SpiNNterceptor is a separate system, currently in the early stages of design, that will build upon SpinLink to address the important external I/O issues faced by SpiNNaker. Specifically, spare resources in the FPGAs will be used to implement the debugging and I/O interfacing features of SpiNNterceptor

Enable++ : a second generation FPGA processor

In the computing community field programmable processors are going to fill the niche for special purpose computing devices. A typical example is ultra-fast pattern recognition in experimental particle physics - a task for which we constructed two years ago Enable- 1, an FPGA processor rather specialized for pattern recognition algorithms in μs domain, but also provided with modest features for coping with more general applications. This paper presents the follow-up modell Enable++, a 2nd generation FPGA processor that offers several substantial enhancements over the previous system for a wider range of applications: Enable++ is structured into three different state-of-the-art modules for providing computing power, flexible and high-speed I/O communication and powerful intermodule communication with a raw bandwidth of 3.2 GByte/s by an active backplane. The technical realization of all three modules is guided by the maximum usage of field programmable logic. The actual demand of computing-and I/O-power can be satisified by the number of modules plugged into the crate. Enhanced features of Enable++ comprise the configurable processor topology provided by programmable crossbar switches. In combination with the 4 x 4 FPGA array and 12 MByte distributed RAM the Enable++ computing core offers a strongly increased and scalable computing power. For building new applications the system offers a comfortable programming and debugging environment consisting of a compiler for the C-like hardware description language spC, a simulator and a source level debugger for hardware design. The goal in planning the hardware design environment for Enable++ from scratch is to transfer established methodologies in software design to the design of digital logic. Concerning pattern recognition tasks, we estimate that Enable++ surpasses modern RISC processors by a factor of 100 to 1000

A mobile data acquisition system

A mobile data aquisition (MobiDAQ) was developed for the ATLAS central hadronic calorimeter (TileCal). MobiDAQ has been designed in order to test the functionalities of the TileCal front-end electronics and to acquire calibration data before the final back-end electronics were built and tested. MobiDAQ was also used to record the first cosmic ray events acquired by an ATLAS subdetector in the underground experimental area

Design and Implementation of a FPGA and DSP Based MIMO Radar Imaging System

The work presented in this paper is aimed at the implementation of a real-time multiple-input multiple-output (MIMO) imaging radar used for area surveillance. In this radar, the equivalent virtual array method and time-division technique are applied to make 16 virtual elements synthesized from the MIMO antenna array. The chirp signal generater is based on a combination of direct digital synthesizer (DDS) and phase locked loop (PLL). A signal conditioning circuit is used to deal with the coupling effect within the array. The signal processing platform is based on an efficient field programmable gates array (FPGA) and digital signal processor (DSP) pipeline where a robust beamforming imaging algorithm is running on. The radar system was evaluated through a real field experiment. Imaging capability and real-time performance shown in the results demonstrate the practical feasibility of the implementation