Stochastic Analysis of Some Expedited Forwarding Networks

We consider stochastic guarantees for networks with aggregate scheduling, in particular, Expedited Forwarding (EF). Our approach is based on the assumption that a node can be abstracted by a service curve, and the input flows are regulated individually at the network ingress. Both of these assumptions are inline with the current definition of EF \cite{charny-00-b,davie-01-a}. We derive bounds to the complementary distributions of the backlog, delay through a single node, and the end-to-end delay. We also give a bound on the loss-ratio. Our analysis is exact under the given assumptions. Our results should help us to understand the performance of networks with aggregate scheduling, and provide the basis for dimensioning such networks

Multiplexing regulated traffic streams: design and performance

The main network solutions for supporting QoS rely on traf- fic policing (conditioning, shaping). In particular, for IP networks the IETF has developed Intserv (individual flows regulated) and Diffserv (only ag- gregates regulated). The regulator proposed could be based on the (dual) leaky-bucket mechanism. This explains the interest in network element per- formance (loss, delay) for leaky-bucket regulated traffic. This paper describes a novel approach to the above problem. Explicitly using the correlation structure of the sources’ traffic, we derive approxi- mations for both small and large buffers. Importantly, for small (large) buffers the short-term (long-term) correlations are dominant. The large buffer result decomposes the traffic stream in a stream of constant rate and a periodic impulse stream, allowing direct application of the Brownian bridge approximation. Combining the small and large buffer results by a concave majorization, we propose a simple, fast and accurate technique to statistically multiplex homogeneous regulated sources. To address heterogeneous inputs, we present similarly efficient tech- niques to evaluate the performance of multiple classes of traffic, each with distinct characteristics and QoS requirements. These techniques, applica- ble under more general conditions, are based on optimal resource (band- width and buffer) partitioning. They can also be directly applied to set GPS (Generalized Processor Sharing) weights and buffer thresholds in a shared resource system

Theories and Models for Internet Quality of Service

We survey recent advances in theories and models for Internet Quality of Service (QoS). We start with the theory of network calculus, which lays the foundation for support of deterministic performance guarantees in networks, and illustrate its applications to integrated services, differentiated services, and streaming media playback delays. We also present mechanisms and architecture for scalable support of guaranteed services in the Internet, based on the concept of a stateless core. Methods for scalable control operations are also briefly discussed. We then turn our attention to statistical performance guarantees, and describe several new probabilistic results that can be used for a statistical dimensioning of differentiated services. Lastly, we review recent proposals and results in supporting performance guarantees in a best effort context. These include models for elastic throughput guarantees based on TCP performance modeling, techniques for some quality of service differentiation without access control, and methods that allow an application to control the performance it receives, in the absence of network support

Advances in Internet Quality of Service

We describe recent advances in theories and architecture that support performance guarantees needed for quality of service networks. We start with deterministic computations and give applications to integrated services, differentiated services, and playback delays. We review the methods used for obtaining a scalable integrated services support, based on the concept of a stateless core. New probabilistic results that can be used for a statistical dimensioning of differentiated services are explained; some are based on classical queuing theory, while others capitalize on the deterministic results. Then we discuss performance guarantees in a best effort context; we review: methods to provide some quality of service in a pure best effort environment; methods to provide some quality of service differentiation without access control, and methods that allow an application to control the performance it receives, in the absence of network support

Architecture for Guaranteed Delay Service in High Speed Networks

The increasing importance of network connections coupled with the lack of abundant link capacity suggests that the day when service guarantees are required by individual connections is not far off. In this dissertation we describe a networking architecture that can efficiently provide end-to-end delay guarantees on a per- connection basis. In order to provide any kind of service guarantee it is imperative for the source traffic to be accurately characterized at the ingress to the network. Furthermore, this characterization should be enforceable through the use of a traffic shaper (or similar device). We go one step further and assume an extensive use of traffic shapers at each of the network elements. Reshaping makes the traffic at each node more predictable and therefore simplifies the task of providing efficient delay guarantees to individual connections. The use of per-connection reshapers to regulate traffic at each hop in the network is referred to as a Rate Controlled Service (RCS) discipline. By exploiting some properties of traffic shapers we demonstrate how the per-hop reshaping does not increase the bound on the end-to-end delay experienced by a connection. In particular, we show that an appropriate choice of traffic shaper parameters enables the RCS discipline to provide better end-to- end delay guarantees than any other service discipline known today. The RCS discipline can provide efficient end-to-end delay guarantees to a connection; however, by definition it is not work-conserving. This fact may increase the average delay that is observed by a connection even if there is no congestion in the network. We outline a mechanism by which an RCS discipline can be modified to be work-conserving without sacrificing the efficient end-to-end delay guarantees that can be provided to individual connections. Using the notion of service curves to bound the service process at each network element, we are able to provide an upper bound on the buffers required to ensure zero loss at the network element. Finally, we examine how the RCS discipline can be used in the context of the Guaranteed Services specification that is currently in the process of being standardized by the Internet Engineering Task Force

Worst Case Latency Analysis for Hoplite FPGA-based NoC

Overlay NoCs, such as Hoplite, are cheap to implement on an FPGA but provide no bounds on worst-case routing latency of packets traversing the NoC due to deflection routing. In this paper, we show how to adapt Hoplite to enable calculation of precise upper bounds on routing latency by modifying the routing function to prioritize deflections, and by regulating the injection of packets to meet certain throughput and burstiness constraints. We provide an analytical model for computing end-to-end latency in the form of (1) in-flight time in the network $T^f$, and (2) waiting time at the source node $T^s$. To bound in-flight time in an $m \times m$ NoC, we modify the routing function and switching crossbar richness in the Hoplite router to deliver $T^{f} =\Delta X + \Delta Y + (\Delta Y \times m) + 2$ where $\Delta X$ and $\Delta Y$ are differences of the source and destination address co-ordinates of the packet. To bound the waiting time at the source, we add a Token Bucket regulator with rate $\rho_i$ and burstiness $\sigma_i$ for each flow $f_i$node $(x,y)$ to deliver $(\lceil\frac{1}{\rho_{_i}}\rceil -1 ) + T^s$ : T^s =\lceil\frac{\sigma(\Gamma^C_f){1-\rho(\Gamma^C_f)} \rceil which depends on the regulator period $1/\rho_i$, burstiness $\sigma$ and the rate $\rho$ of all interfering flows $\Gamma^C_f$. A 64b implementation of our HopliteRT routerrequires $\approx$4\% fewer LUTs, and similar number of FFs compared to the original Hoplite router. We also need two small counters at each client port for regulating injection. We evaluate our model and RTL implementation across synthetic traffic patterns and observe behavior that conforms with the analytical bounds

HopliteBuf FPGA Network-on-Chip: Architecture and Analysis

We can prove occupancy bounds of stall-free FIFOs used in deflection-free, low-cost, and high-speed FPGA overlay Network-on-chips (NoCs). In our work, we build on top of the HopliteRT livelock-free overlay NoC with an FPGA-friendly 2D unidirectional torus topology to propose the novel HopliteBuf NoC. In our new NoC, we strategically introduce stall-free FIFOs in the network and support these FIFOs with static analysis based on network calculus to compute FIFO occupancy, latency, and bandwidth bounds. The microarchitecture of HopliteBuf combines the performance benefits of conventional buffered NoCs (high throughput, low latency) with the cost advantages of deflection-routed NoCs (low FPGA area, high clock frequencies). Specifically, we look at two design variants of the HopliteBuf NoC: (1) Single corner-turn FIFO (W to S), and (2) Dual corner-turn FIFO (W to S+N). The single corner-turn (W to S) design is simpler and only introduces a buffering requirement for packets changing dimension from X ring to the downhill Y ring (or West to South). The dual corner-turn variant requires two FIFOs for turning packets going downhill (W to S) as well as uphill (W to N). The dual corner-turn design overcomes the mathematical analysis challenges associated with single corner-turn designs for communication workloads with cyclic dependencies between flow traversal paths at the expense of small increase in resource cost. Essentially, we resolve an analysis challenge with extra hardware resources. Across a range of 100 synthetically-generated workloads on a 5 x 5 NoC, HopliteBuf outperforms HopliteRT by 1.2-2x in terms of latency, 10% in terms of injection rate, and 30-60% in terms of flowset feasibiliy. These advantages come at the cost of 3-4x higher FPGA resource requirement for buffers and muxes. Our analysis also deliver latency bounds that are not only better than HopliteRT in absolute terms but also tighter by 2-3x allowing us to provision less hardware to meet our specifications