Silicon circuits for chip-to-chip communications in multi-socket server board interconnects

Multi-socket server boards (MSBs) exploit the interconnection of multiple processor chips towards forming powerful cache coherent systems, with the interconnect technology comprising a key element in boosting processing performance. Here, we present an overview of the current electrical interconnects for MSBs, outlining the main challenges currently faced. We propose the use of silicon photonics (SiPho) towards advancing interconnect throughput, socket connectivity and energy efficiency in MSB layouts, enabling a flat-topology wavelength division multiplexing (WDM)-based point-to-point (p2p) optical MSB interconnect scheme. We demonstrate WDM SiPho transceivers (TxRxs) co-assembled with their electronic circuits for up to 50 Gb/s line rate and 400 Gb/s aggregate data transmission and SiPho arrayed waveguide grating routers that can offer collision-less time of flight connectivity for up to 16 nodes. The capacity can scale to 2.8 Gb/s for an eight-socket MSB, when line rate scales to 50 Gb/s, yielding up to 69% energy reduction compared with the QuickPath Interconnect and highlighting the feasibility of single-hop p2p interconnects in MSB systems with >4 sockets

A 40 Gb/s chip-to-chip interconnect for 8-socket direct connectivity using integrated photonics

We present an O-band any-to-any chip-to-chip (C2C) interconnection at 40 Gb/s suitable for up to 8-socket direct connectivity in multi-socket server boards, utilizing integrated low-energy photonics for the transceiver and routing functions. The C2C interconnect exploits an Si-based ring modulator as its transmitter and a co-packaged photodiode/transimpedance amplifier enabled receiver interconnected over an 8 x 8 Si-based arrayed waveguide grating router, allowing for a single-hop flat-topology interconnection between eight nodes. A proof-of-concept demonstration of the C2C interconnect is presented at 25 and 40 Gb/s for eight possible routing scenarios, revealing clear eye diagrams at both data rates with extinction ratios of 4.8 +/- 0.3 and 4.38 +/- 0.31 dB, respectively, among the eight routed signals

Network-on-Chip

Addresses the Challenges Associated with System-on-Chip Integration Network-on-Chip: The Next Generation of System-on-Chip Integration examines the current issues restricting chip-on-chip communication efficiency, and explores Network-on-chip (NoC), a promising alternative that equips designers with the capability to produce a scalable, reusable, and high-performance communication backbone by allowing for the integration of a large number of cores on a single system-on-chip (SoC). This book provides a basic overview of topics associated with NoC-based design: communication infrastructure design, communication methodology, evaluation framework, and mapping of applications onto NoC. It details the design and evaluation of different proposed NoC structures, low-power techniques, signal integrity and reliability issues, application mapping, testing, and future trends. Utilizing examples of chips that have been implemented in industry and academia, this text presents the full architectural design of components verified through implementation in industrial CAD tools. It describes NoC research and developments, incorporates theoretical proofs strengthening the analysis procedures, and includes algorithms used in NoC design and synthesis. In addition, it considers other upcoming NoC issues, such as low-power NoC design, signal integrity issues, NoC testing, reconfiguration, synthesis, and 3-D NoC design. This text comprises 12 chapters and covers: The evolution of NoC from SoC—its research and developmental challenges NoC protocols, elaborating flow control, available network topologies, routing mechanisms, fault tolerance, quality-of-service support, and the design of network interfaces The router design strategies followed in NoCs The evaluation mechanism of NoC architectures The application mapping strategies followed in NoCs Low-power design techniques specifically followed in NoCs The signal integrity and reliability issues of NoC The details of NoC testing strategies reported so far The problem of synthesizing application-specific NoCs Reconfigurable NoC design issues Direction of future research and development in the field of NoC Network-on-Chip: The Next Generation of System-on-Chip Integration covers the basic topics, technology, and future trends relevant to NoC-based design, and can be used by engineers, students, and researchers and other industry professionals interested in computer architecture, embedded systems, and parallel/distributed systems

Boosting multi-socket cache-coherency with low-latency silicon photonic interconnects

Speed-up in computing systems today is most often accomplished by increasing parallelism in both hardware and software. Parallel applications residing wholly on a single multi-core chip generally utilize implicit inter-thread communication via shared memory managed by cache-coherency mechanisms. However, increasing parallelism by creating coherent domains across many chips poses new challenges. In this work, we illustrate the sensitivity of various applications on a theoretical four-socket system to the latency of their coherency traffic, and show that current solutions, such as Quick Path Interconnect (QPI) and HyperTransport (HT), could benefit greatly from a lower latency communication medium. Then, we propose a silicon photonic inter-chip network that achieves very low-latency and falls within a reasonable power budget