Teaching Asynchronous Digital Design in the Undergraduate Computer Engineering Curriculum

As demand continues for circuits with higher performance, higher complexity, and decreased feature size, asynchronous (clockless) paradigms will become more widely used in the semiconductor industry, as evidenced by the International Technology Roadmap for Semiconductors\u27 (ITRS) prediction of a likely shift from synchronous to asynchronous design styles in order to increase circuit robustness, decrease power, and alleviate many clock-related issues. ITRS predicts that asynchronous circuits will account for 19% of chip area within the next 5 years, and 30% of chip area within the next 10 years. To meet this growing industry need, students in Computer Engineering should be introduced to asynchronous circuit design to make them more marketable and more prepared for the challenges faced by the digital design community for years to come

Asynchronous Logic Circuits and Sheaf Obstructions

AbstractThis article exhibits a particular encoding of logic circuits into a sheaf formalism. The central result of this article is that there exists strictly more information available to a circuit designer in this setting than exists in static truth tables, but less than exists in event-level simulation. This information is related to the timing behavior of the logic circuits, and thereby provides a “bridge” between static logic analysis and detailed simulation

Area/latency optimized early output asynchronous full adders and relative-timed ripple carry adders

This article presents two area/latency optimized gate level asynchronous full adder designs which correspond to early output logic. The proposed full adders are constructed using the delay-insensitive dual-rail code and adhere to the four-phase return-to-zero handshaking. For an asynchronous ripple carry adder (RCA) constructed using the proposed early output full adders, the relative-timing assumption becomes necessary and the inherent advantages of the relative-timed RCA are: (1) computation with valid inputs, i.e., forward latency is data-dependent, and (2) computation with spacer inputs involves a bare minimum constant reverse latency of just one full adder delay, thus resulting in the optimal cycle time. With respect to different 32-bit RCA implementations, and in comparison with the optimized strong-indication, weak-indication, and early output full adder designs, one of the proposed early output full adders achieves respective reductions in latency by 67.8, 12.3 and 6.1 %, while the other proposed early output full adder achieves corresponding reductions in area by 32.6, 24.6 and 6.9 %, with practically no power penalty. Further, the proposed early output full adders based asynchronous RCAs enable minimum reductions in cycle time by 83.4, 15, and 8.8 % when considering carry-propagation over the entire RCA width of 32-bits, and maximum reductions in cycle time by 97.5, 27.4, and 22.4 % for the consideration of a typical carry chain length of 4 full adder stages, when compared to the least of the cycle time estimates of various strong-indication, weak-indication, and early output asynchronous RCAs of similar size. All the asynchronous full adders and RCAs were realized using standard cells in a semi-custom design fashion based on a 32/28 nm CMOS process technology

Design of an FPGA Logic Element for Implementing Asynchronous NULL Convention Logic Circuits

Two versions of a reconfigurable logic element are developed for use in constructing afield-programmable gate array NULL convention logic (NCL) field-programmable gate array (FPGA): one with extra embedded registration capability, which requires additional area, and one without. Both versions can be configured as any of the 27 fundamental NCL gates, including resettable and inverting variations, and both can utilize embedded registration for gates with three or fewer inputs; however, only the version with the additional embedded registration capability can utilize embedded registration with four-input gates. These two approaches are compared with each other and with an existing approach, showing that both versions developed herein yield a more area efficient NCL circuit implementation, compared to the previous work. The two FPGA logic elements are simulated at the transistor level using the 1.8-V, 180-nm TSMC CMOS process

Speck: A Smart event-based Vision Sensor with a low latency 327K Neuron Convolutional Neuronal Network Processing Pipeline

Edge computing solutions that enable the extraction of high level information from a variety of sensors is in increasingly high demand. This is due to the increasing number of smart devices that require sensory processing for their application on the edge. To tackle this problem, we present a smart vision sensor System on Chip (Soc), featuring an event-based camera and a low power asynchronous spiking Convolutional Neuronal Network (sCNN) computing architecture embedded on a single chip. By combining both sensor and processing on a single die, we can lower unit production costs significantly. Moreover, the simple end-to-end nature of the SoC facilitates small stand-alone applications as well as functioning as an edge node in a larger systems. The event-driven nature of the vision sensor delivers high-speed signals in a sparse data stream. This is reflected in the processing pipeline, focuses on optimising highly sparse computation and minimising latency for 9 sCNN layers to $3.36\mu s$. Overall, this results in an extremely low-latency visual processing pipeline deployed on a small form factor with a low energy budget and sensor cost. We present the asynchronous architecture, the individual blocks, the sCNN processing principle and benchmark against other sCNN capable processors

Lazy transition systems: application to timing optimization of asynchronous circuits

The paper introduces Lazy Transitions Systems (LzTSs). The notion of laziness explicitly distinguishes between the enabling and the firing of an event in a transition system. LzTSs can be effectively used to model the behavior of asynchronous circuits in which relative timing assumptions can be made on the occurrence of events. These assumptions can be derived from the information known a priori about the delay of the environment and the timing characteristics of the gates that will implement the circuit. The paper presents necessary conditions to synthesize circuits with a correct behavior under the given timing assumptions. Preliminary results show that significant area and performance improvements can be obtained by exploiting the extra "don't care" space implicitly provided by the laziness of the events.Peer ReviewedPostprint (author's final draft

Design of Asynchronous Circuits for High Soft Error Tolerance in Deep Submicron CMOS Circuits

As the devices are scaling down, the combinational logic will become susceptible to soft errors. The conventional soft error tolerant methods for soft errors on combinational logic do not provide enough high soft error tolerant capability with reasonably small performance penalty. This paper investigates the feasibility of designing quasi-delay insensitive (QDI) asynchronous circuits for high soft error tolerance. We analyze the behavior of null convention logic (NCL) circuits in the presence of particle strikes, and propose an asynchronous pipeline for soft-error correction and a novel technique to improve the robustness of threshold gates, which are basic components in NCL, against particle strikes by using Schmitt trigger circuit and resizing the feedback transistor. Experimental results show that the proposed threshold gates do not generate soft errors under the strike of a particle within a certain energy range if a proper transistor size is applied. The penalties, such as delay and power consumption, are also presented

Automatic synthesis of fast compact self-timed control circuits

Journal ArticleWe present a tool called MEAT which has been designed to automatically synthesize transistor level. CMOS, self-timed control circuits. MEAT has been used to specify and synthesize self-timed circuits for a fully self-timed 300,000 transistor communication coprocessor. The design is specified using finite state machines which permit burst-mode inputs. Burst-mode is a limited form of MIC (multiple input change) signalling. The primary goal of MEAT is to produce fast and compact circuits. In order to achieve this goal, MEAT implementations permit timing assumption which can by verifiably supported at the physical implementation level, and result in significant improvements in speed and area of the design. Since MEAT has been used for large designs, we have also been forced to make the algorithms efficient. The result is a tool which is efficient, easy to use by today's hardware designers since the specification is based on the commonly used finite state machine control model, and synthesize CMOS transistor implementations that are self-timed, fast and compact. The paper presents a description of the tool, the nature of the algorithms used, and examples of its use