Bandwidth-Constrained Mapping of Cores onto NoC Architectures

We address the design of complex monolithic systems, where processing cores generate and consume a varying and large amount of data, thus bringing the communication links to the edge of congestion. Typical applications are in the area of multi-media processing. We consider a mesh-based Networks on Chip (NoC) architecture, and we explore the assignment of cores to mesh cross-points so that the traffic on links satisfies bandwidth constraints. A single-path deterministic routing between the cores places high bandwidth demands on the links. The bandwidth requirements can be significantly reduced by splitting the traffic between the cores across multiple paths. In this paper, we present NMAP, a fast algorithm that maps the cores onto a mesh NoC architecture under bandwidth constraints, minimizing the average communication delay. The NMAP algorithm is presented for both single minimum-path routing and split-traffic routing. The algorithm is applied to a benchmark DSP design and the resulting NoC is built and simulated at cycle accurate level in SystemC using macros from the ?pipes library. Also, experiments with six video processing applications show significant savings in bandwidth and communication cost for NMAP algorithm when compared to existing algorithms

Task mapping and routing optimization for hard real-time Networks-on-Chip

Interference from high priority tasks and messages in a hard real-time Networks-on-Chip (NoC) create computation and communication delays. As the delays increase in number, maintaining the system’s schedulability become difficult. In order to overcome the problem, one way is to reduce interference in the NoC by changing task mapping and network routing. Some population-based heuristics evaluate the worst-case response times of tasks and messages based on the schedulability analysis, but requires a significant amount of optimization time to complete due to the complexity of the evaluation function. In this paper, we propose an optimization technique that explore both parameters simultaneously with the aim to meet the schedulability of the system, hence reducing the optimization time. One of the advantages from our approach is the unrepeated call to the evaluation function, which is unaddressed in the heuristics that configure design parameters in stages. The results show that a schedulable configuration can be found from the large design space

Програмна модель мереж на кристалі із нерегулярними топологіями

The review of different approaches to the simulation of the networks-on-chip (NoC) is performed. The simulator of the NoC where the topology is set with the matrix of connections between the routers that manage the traffic by means of the routing tables is developed. The capabilities of the NoC simulator are examined and the results of its approbation by the example of the regular and quasi-optimal NoCs are presentedПроведен обзор различных подходов к моделированию сетей на кристалле (СтнК). Разработан симулятор СтнК, где топология задается матрицей связей между роутерами, которые управляют трафиком с помощью таблиц маршрутизации. Рассмотрены возможности симулятора СтнК и представлены результаты его апробации на примере регулярных и квазиоптимальных сетейПроведено огляд різних підходів до моделювання мереж на кристалі (МнК). Розроблено симулятор МнК, у якому топологія задається матрицею зв’язків між роутерами, що керують трафіком за допомогою таблиць маршрутизації. Розглянуто можливості симулятора МнК та представлені результати його апробації на прикладі регулярних і квазіоптимальних мере

Power Optimization for Mesh Network-on-Chip Architecture: Multilevel Network Partitioning Approach

This paper presents a power optimization for mesh Network-on-Chip (NoC) architecture by using Multilevel Network Partitioning approach. Power consumption is reduced by re-dividing the large networks into few smaller partitions. This approach assigns excessively communicated Intellectual Property (IP) cores into the same portion that result the minimal average inter-core distance. The efficiency of this methodology is verified through a System-on-Chip (SoC) application known as Video Object Plan Decoder (VOPD). Experimental results show a promising improvement of 16.59% in the power consumption

SMART: A Single-Cycle Reconfigurable NoC for SoC Applications

As technology scales, SoCs are increasing in core counts, leading to the need for scalable NoCs to interconnect the multiple cores on the chip. Given aggressive SoC design targets, NoCs have to deliver low latency, high bandwidth, at low power and area overheads. In this paper, we propose Single-cycle Multi-hop Asynchronous Repeated Traversal (SMART) NoC, a NoC that reconfigures and tailors a generic mesh topology for SoC applications at runtime. The heart of our SMART NoC is a novel low-swing clockless repeated link circuit embedded within the router crossbars, that allows packets to potentially bypass all the way from source to destination core within a single clock cycle, without being latched at any intermediate router. Our clockless repeater link has been proven in silicon in 45nm SOI. Results show that at 2GHz, we can traverse 8mm within a single cycle, i.e. 8 hops with 1mm cores. We implement the SMART NoC to layout and show that SMART NoC gives 60% latency savings, and 2.2X power savings compared to a baseline mesh NoC.United States. Defense Advanced Research Projects Agency. The Ubiquitous High-Performance Computing Progra

Анализ подходов к синтезу сетей на кристалле с использованием регулярных топологий

The article gives a review of existing methods of networks-on-chip design, based on the approach, in which the projection of the characteristic tasks graph is performed on a given regular topology. The general problem of the synthesis of networks-on-chip is characterized. The network topology can be foreknown (usually a regular topology) or selected in accordance with the tasks that will be performed by the network-on-chip. The first method of synthesis of networks-on-chip is widespread among the developers due to its relative simplicity and obviousness and presented in a variety of implementations, which are reviewed in this article. The advantages and disadvantages of this approach, the effect achieved by its application to various implementations of networks-on-chip and the way of its improvement, which is to extend the scope of solutions for regular network topologies on the predetermined irregular topologies with better characteristics are offered.В статье выполнен обзор существующих способов проектирования сетей на кристалле, основанных на подходе, при котором осуществляется проекция характеристического графа задачи на заданную регулярную топологию. Охарактеризована общая задача синтеза сетей на кристалле. Топология сети может быть заранее известной (обычно это регулярная топология) или выбирается в зависимости от задачи, которая будет выполняться сетью на кристалле. Первый способ синтеза сетей на кристалле благодаря своей относительной простоте и очевидности получил большое распространение среди разработчиков и представлен во множестве реализаций, обзор которых проведен в данной статье. Показаны преимущества и недостатки данного подхода, достигнутый эффект от его применения для различных реализаций сетей на кристалле, а также предложен путь его усовершенствования, который заключается в том, чтобы расширить область применения решений для регулярных топологий сетей на заранее заданные нерегулярные топологии с лучшими характеристиками

An ILP formulation for application mapping onto Network-on-Chips

Ever shrinking technologies in VLSI era made it possible to place several modules onto a single die. However, the need for the new communication methods has also increased dramatically since traditional bus-based systems suffer from signal propagation delays, signal integrity, and scalability. Network-on-Chip (NoC) is the biggest step towards the communication bottleneck of System-on-Chip (SoC) architectures. In this paper, we present an Integer Linear Programming (ILP) formulation for application mapping onto mesh based Network-on-Chips to minimize the energy consumption of the system. The proposed method obtains optimal or close to optimal results within the given computation time limit. We also experimentally investigate the impact of the size of the mesh architecture on the application mapping and total communication. ©2009 IEEE