HDL slicing for verification and test

textThe semiconductor industry has been increasingly relying on computer-aided design (CAD) tools in order to meet its demand for high performance and stringent time-to-market requirements. However, practical application of state-of-the-art CAD tools is severely limited by the sheer size of the design sizes. Therefore, an appropriate methodology that exploits the inherent modular structure within the complex designs, is desired. This dissertation proposes such a methodology that is useful with a variety of CAD tools in design verification and manufacturing test generation. Functional test generation using sequential automatic test pattern generation (ATPG) tools is extremely computation intensive and produces acceptable results only on relatively small designs. Therefore, hierarchical approaches are necessary to reduce the ATPG complexity. A promising approach was previously proposed in which individual modules in a design are targeted one at a time, using an ad-hoc abstraction for the reminder of the design derived from its register-transfer level (RTL) model. Based on this approach, an elegant and a systematic approach based on “program slicing”, that allows it to be scalable for large designs, is developed. The theoretical basis for applying program slicing on hardware description languages (HDLs) is established, and a tool called FACTOR has been implemented to automate the approach for test generation and testability analysis. Design verification requires exploring the complete design space to ensure the correctness of the design. A proof-by-contradiction approach called bounded model checking (BMC) has been proposed, which utilizes satisfiability (SAT) capabilities to find counterexamples for temporal properties within a specified number of time steps. The proposed scheme harnesses the power of sequential-ATPG tools to use structural information of a hardware design, to perform BMC more efficiently. This approach has been further augmented by the HDL slicing methodology for test generation, to accelerate the verification methodology. Symbolic simulation uses symbols rather than actual values for simulating a hardware design, so that the responses to a class of values can be computed and checked for correctness in a single run. The effectiveness of this approach has been incorporated into a powerful verification methodology, called symbolic trajectory evaluation (STE), to verify properties of bounded state sequences, intermixed with properties of invariant behavior. Assertions are described in a limited form of temporal logic and are symbolically validated against the design under verification. The HDL slicing tool, FACTOR, has been appropriately applied to speed up the verification of the floating point adder-subtractor unit of the Pentium 4 design in Intel’s Forte verification framework.Electrical and Computer Engineerin

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Towards the Evolution of Novel Vertical-Axis Wind Turbines

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Behavioral synthesis involves compiling an Electronic System-Level (ESL) design into its Register-Transfer Level (RTL) implementation. Loop pipelining is one of the most critical and complex transformations employed in behavioral synthesis. Certifying the loop pipelining algorithm is challenging because there is a huge semantic gap between the input sequential design and the output pipelined implementation making it infeasible to verify their equivalence with automated sequential equivalence checking techniques. We discuss our ongoing effort using ACL2 to certify loop pipelining transformation. The completion of the proof is work in progress. However, some of the insights developed so far may already be of value to the ACL2 community. In particular, we discuss the key invariant we formalized, which is very different from that used in most pipeline proofs. We discuss the needs for this invariant, its formalization in ACL2, and our envisioned proof using the invariant. We also discuss some trade-offs, challenges, and insights developed in course of the project.Comment: In Proceedings ACL2 2014, arXiv:1406.123

gCSP: A Graphical Tool for Designing CSP systems

For broad acceptance of an engineering paradigm, a graphical notation and a supporting design tool seem necessary. This paper discusses certain issues of developing a design environment for building systems based on CSP. Some of the issues discussed depend specifically on the underlying theory of CSP, while a number of them are common for any graphical notation and supporting tools, such as provisions for complexity management and design overview