4 research outputs found
Microcomputer Based Simulation
Digital simulation is a useful tool in many scientific areas.
Interactive simulation can provide the user with a better appreciation
of a problem area. With the introduction of large scale integrated
circuits and in particular the advent of the microprocessor, a large
amount of computing power is available at low cost. The aim of
this project therefore was to investigate the feasibility of producing
a minimum cost, easy to use, interactive digital simulation system.
A hardware microcomputer system was constructed to test simulation
program concepts and an interactive program was designed and developed
for this system. By the use of a set of commands and subsequent
interactive dialogue, the program allows the user to enter and perform
simulation tasks. The simulation program is unusual in that it does
not require a sophisticated operating system or other system programs
such as compilers. The program does not require any backup memory
devices such as magnetic disc or tape and indeed could be stored in
ROM or EPROM. The program is designed to be flexible and extendable
and could be easily modified to run with a variety of hardware configurations.
The highly interactive nature of the system means that
its operation requires very little programming experience.
The microcomputer hardware system uses two microprocessors
together with specially designed interfaces. One was dedicated to
the implementation of the simulation equations, and the other
provided an input/output capability including a low cost CRT display
Software implemented fault tolerance for microprocessor controllers: fault tolerance for microprocessor controllers
It is generally accepted that transient faults are a major cause of failure in micro processor systems. Industrial controllers with embedded microprocessors are particularly at risk from this type of failure because their working environments are prone to transient disturbances which can generate transient faults. In order to improve the reliability of processor systems for industrial applications within a limited budget, fault tolerant techniques for uniprocessors are implemented. These techniques aim to identify characteristics of processor operation which are attributed to erroneous behaviour. Once detection is achieved, a programme of restoration activity can be initiated. This thesis initially develops a previous model of erroneous microprocessor behaviour from which characteristics particular to mal-operation are identified. A new technique is proposed, based on software implemented fault tolerance which, by recognizing a particular behavioural characteristic, facilitates the self-detection of erroneous execution. The technique involves inserting detection mechanisms into the target software. This can be quite a complex process and so a prototype software tool called Post-programming Automated Recovery UTility (PARUT) is developed to automate the technique's application. The utility can be used to apply the proposed behavioural fault tolerant technique for a selection of target processors. Fault injection and emulation experiments assess the effectiveness of the proposed fault tolerant technique for three application programs implemented on an 8, 16, and 32- bit processors respectively. The modified application programs are shown to have an improved detection capability and hence reliability when the proposed fault tolerant technique is applied. General assessment of the technique cannot be made, however, because its effectiveness is application specific. The thesis concludes by considering methods of generating non-hazardous application programs at the compilation stage, and design features for incorporation into the architecture of a microprocessor which inherently reduce the hazard, and increase the detection capability of the target software. Particular suggestions are made to add a 'PARUT' phase to the translation process, and to orientate microprocessor design towards the instruction opcode map
Display controller architectures for computer graphics
The currently prevalent forms of display controller hardware are discussed in terms of their architecture, and their relationship to the software which forms the graphics packages with which they are to be used. New architectures are proposed utilising both conventional, commercially available components and special purpose Large Scale Integrated circuits. The concept of a "hardware graphics package" Is developed and implementation details presented. The conclusions drawn from this work are that in order to provide an appropriate environment for the type of interactive graphics capabilities which will form the hub of much future software, more emphasis must be placed on intelligent display systems. This distributed approach requires that a host computer provides a display controller with a high-level scene description which is subsequently rendered to constituent polygonal facets by the controller. Substantial benefits accrue from this reduced dependence upon a single Central Processing element