An Automated Design-flow for FPGA-based Sequential Simulation

In this paper we describe the automated design flow that will transform and map a given homogeneous or heterogeneous hardware design into an FPGA that performs a cycle accurate simulation. The flow replaces the required manually performed transformation and can be embedded in existing standard synthesis flows. Compared to the earlier manually translated designs, this automated flow resulted in a reduced number of FPGA hardware resources and higher simulation frequencies. The implementation of the complete design flow is work in progress.\u

Synthesizing Certified Code

Code certification is a lightweight approach for formally demonstrating software quality. Its basic idea is to require code producers to provide formal proofs that their code satisfies certain quality properties. These proofs serve as certificates that can be checked independently. Since code certification uses the same underlying technology as program verification, it requires detailed annotations (e.g., loop invariants) to make the proofs possible. However, manually adding annotations to the code is time-consuming and error-prone. We address this problem by combining code certification with automatic program synthesis. Given a high-level specification, our approach simultaneously generates code and all annotations required to certify the generated code. We describe a certification extension of AutoBayes, a synthesis tool for automatically generating data analysis programs. Based on built-in domain knowledge, proof annotations are added and used to generate proof obligations that are discharged by the automated theorem prover E-SETHEO. We demonstrate our approach by certifying operator- and memory-safety on a data-classification program. For this program, our approach was faster and more precise than PolySpace, a commercial static analysis tool

An automatic tool flow for the combined implementation of multi-mode circuits

A multi-mode circuit implements the functionality of a limited number of circuits, called modes, of which at any given time only one needs to be realised. Using run-time reconfiguration of an FPGA, all the modes can be implemented on the same reconfigurable region, requiring only an area that can contain the biggest mode. Typically, conventional run-time reconfiguration techniques generate a configuration for every mode separately. To switch between modes the complete reconfigurable region is rewritten, which often leads to very long reconfiguration times. In this paper we present a novel, fully automated tool flow that exploits similarities between the modes and uses Dynamic Circuit Specialization to drastically reduce reconfiguration time. Experimental results show that the number of bits that is rewritten in the configuration memory reduces with a factor from 4.6X to 5.1X without significant performance penalties

Global design of analog cells using statistical optimization techniques

We present a methodology for automated sizing of analog cells using statistical optimization in a simulation based approach. This methodology enables us to design complex analog cells from scratch within reasonable CPU time. Three different specification types are covered: strong constraints on the electrical performance of the cells, weak constraints on this performance, and design objectives. A mathematical cost function is proposed and a bunch of heuristics is given to increase accuracy and reduce CPU time to minimize the cost function. A technique is also presented to yield designs with reduced variability in the performance parameters, under random variations of the transistor technological parameters. Several CMOS analog cells with complexity levels up to 48 transistors are designed for illustration. Measurements from fabricated prototypes demonstrate the suitability of the proposed methodology

Thermally stable low current consuming gallium and germanium chalcogenides for consumer and automotive memory applications

The phase change technology behind rewritable optical disks and the latest generation of electronic memories has provided clear commercial and technological advances for the field of data storage, by virtue of the many well known attributes, in particular scaling, cycling endurance and speed, that chalcogenide materials offer. While the switching power and current consumption of established germanium antimony telluride based memory cells are a major factor in chip design in real world applications, often the thermal stability of the device can be a major obstacle in the path to the full commercialisation. In this work we describe our research in material discovery and characterization for the purpose of identifying more thermally stable chalcogenides for applications in PCRAM

Circuit topology and synthesis flow co-design for the development of computational ReRAM

© 2022 IEEE. Personal use of this material is permitted. Permission from IEEE must be obtained for all other uses, in any current or future media, including reprinting/republishing this material for advertising or promotional purposes,creating new collective works, for resale or redistribution to servers or lists, or reuse of any copyrighted component of this work in other works.Emerging memory technologies will play a decisive role in the quest for more energy-efficient computing systems. Computational ReRAM structures based on resistive switching devices (memristors) have been explored for in-memory computations using the resistance of ReRAM cells for storage and for logic I/O representation. Such approach presents three major challenges: the support for a memristor-oriented logic style, the ad-hoc design of memory array driving circuitry for memory and logic operations, and the development of dedicated synthesis tools to instruct the multi-level operations required for the execution of an arbitrary logic function in memory. This work contributes towards the development of an automated design flow for ReRAM-based computational memories, highlighting some important HW-SW co-design considerations. We briefly present a case study concerning a synthesis flow for a nonstateful logic style and the co-design of the underlying 1T1R crossbar array driving circuit. The prototype of the synthesis flow is based on the ABC tool and the Z3 solver. It executes fast owing to the level-by-level mapping of logic gates. Moreover, it delivers a mapping that minimizes the logic function latency through parallel logic operations, while also using the less possible ReRAM cells.Supported by Synopsys, Chile, by the Chilean grants FONDECYT Regular 1221747 and ANID-Basal FB0008, and by the Spanish MCIN/AEI/10.13039/501100011033 grant PID2019-103869RB-C33Peer ReviewedPostprint (author's final draft