Asynchronous techniques for new generation variation-tolerant FPGA

PhD ThesisThis thesis presents a practical scenario for asynchronous logic implementation that would benefit the modern Field-Programmable Gate Arrays (FPGAs) technology in improving reliability. A method based on Asynchronously-Assisted Logic (AAL) blocks is proposed here in order to provide the right degree of variation tolerance, preserve as much of the traditional FPGAs structure as possible, and make use of asynchrony only when necessary or beneficial for functionality. The newly proposed AAL introduces extra underlying hard-blocks that support asynchronous interaction only when needed and at minimum overhead. This has the potential to avoid the obstacles to the progress of asynchronous designs, particularly in terms of area and power overheads. The proposed approach provides a solution that is complementary to existing variation tolerance techniques such as the late-binding technique, but improves the reliability of the system as well as reducing the design’s margin headroom when implemented on programmable logic devices (PLDs) or FPGAs. The proposed method suggests the deployment of configurable AAL blocks to reinforce only the variation-critical paths (VCPs) with the help of variation maps, rather than re-mapping and re-routing. The layout level results for this method's worst case increase in the CLB’s overall size only of 6.3%. The proposed strategy retains the structure of the global interconnect resources that occupy the lion’s share of the modern FPGA’s soft fabric, and yet permits the dual-rail iv completion-detection (DR-CD) protocol without the need to globally double the interconnect resources. Simulation results of global and interconnect voltage variations demonstrate the robustness of the method

Single Photon Interferometry and Quantum Astrophysics

abstract: This thesis contains an overview, as well as the history of optical interferometers. A new approach to interferometric measurements of stars is proposed and explored. Modern updates to the classic techniques are described along with some theoretical derivations showing why the method of single photon counting shows significant promise relative to the currently used amplitude interferometry. Description of a modular intensity interferometer system using commercially available single-photon detectors is given. Calculations on the sensitivity and \emph{uv}-plane coverage using these modules mounted on existing telescopes on Kitt Peak, Arizona is presented. Determining fundamental stellar properties is essential for testing models of stellar evolution as well as for deriving physical properties of transiting exoplanets. The proposed method shows great promise in measuring the angular size of stars. Simulations indicate that it is possible to measure stellar diameters of bright stars with AB magnitude 5% in a single night of observation. Additionally, a description is given of a custom time-to-digital converter designed to time tag individual photons from multiple single-photon detectors with high count rate, continuous data logging, and low systematics. The instrument utilizes a tapped-delay line approach on an FPGA chip which allows for sub-clock resolution of <100 ps. The TDC is implemented on a Re-configurable Open Architecture Computing Hardware Revision 2 (ROACH2) board which allows for continuous data streaming and time tagging of up to 20 million events per second. The functioning prototype is currently set-up to work with up to ten independent channels. Laboratory characterization of the system, including RF, pick up and mitigation, as well as measurement of in-lab photon correlations from an incoherent light source (artificial star), are presented. Additional improvements to the TDC will also be discussed, such as improving the data transfer rate by a factor of 10 via an SDP+ Mezzanine card and PCIe 2SFP+ 10 Gb card, as well as scaling to 64 independent channels. Furthermore, a modified nulling interferometer with image inversion is proposed, for direct imaging of exoplanets below the canonical Rayleigh resolution limit. Image inversion interferometry relies on splitting incoming radiation from a source, either spatially rotating or reflecting the electric field from one arm of the interferometer before recombining the signals and detecting the resulting images in the two output ports with an array of high-speed single-photon detectors. Sources of incoming radiation that have cylindrical symmetry and are centered on the rotation axis will cancel in one of the output ports and add in the other output port. The ability to suppress light from a host star, as well as the ability to resolve past the Rayleigh limit, enables sensitive detection of exoplanets from a stable environment without the need for a coronagraph. The expected number of photons and the corresponding variance in the measurement for different initial contrast ratios are shown, with some first-order theoretical instrumental errors. Lastly, preliminary results from a sizeable photometric survey are presented. This survey is used to derive bolometric flux alongside from angular size measurements and the effective stellar temperatures.Dissertation/ThesisDoctoral Dissertation Astrophysics and Astronomy 201

Generalized reconfigurable memristive dynamical system (MDS) for neuromorphic applications

This study firstly presents (i) a novel general cellular mapping scheme for two dimensional neuromorphic dynamical systems such as bio-inspired neuron models, and (ii) an efficient mixed analog-digital circuit, which can be conveniently implemented on a hybrid memristor-crossbar/CMOS platform, for hardware implementation of the scheme. This approach employs 4n memristors and no switch for implementing an n-cell system in comparison with 2n2 memristors and 2n switches of a Cellular Memristive Dynamical System (CMDS). Moreover, this approach allows for dynamical variables with both analog and one-hot digital values opening a wide range of choices for interconnections and networking schemes. Dynamical response analyses show that this circuit exhibits various responses based on the underlying bifurcation scenarios which determine the main characteristics of the neuromorphic dynamical systems. Due to high programmability of the circuit, it can be applied to a variety of learning systems, real-time applications, and analytically indescribable dynamical systems. We simulate the FitzHugh-Nagumo (FHN), Adaptive Exponential (AdEx) integrate and fire, and Izhikevich neuron models on our platform, and investigate the dynamical behaviors of these circuits as case studies. Moreover, error analysis shows that our approach is suitably accurate. We also develop a simple hardware prototype for experimental demonstration of our approach.Unión Europea H2020 ECOMODE project under grant agreement 604102Unión Europea HBP project under grant number FP7-ICT-2013-FET-F-60410

Live Wire - A Low-Complexity Body Channel Communication System for Landmark Identification

This paper presents a robust simplex Body Channel Communication (BCC) system aimed at providing an interactive infrastructure solution for visually impaired people. Compared to existing BCC solutions, it provides high versatility, weara- bility and installability in an environment in a low complexity hardware-software solution. It operates with a ground referred transmitter (TX) and it is based on an asynchronous thresh- old receiver (RX) architecture. Synchronization, demodulation and packetizing and threshold control are completely software defined and implemented using MicroPython. The RX includes Bluetooth® (BT) radio connectivity and a cell-phone application provides push text-to-speech notifications to a smartphone. The hardware achieves a Packet Error Rate (PER) of ∼0.1 at 550 kHz pulse center frequency, Synchronized-On Off Keying (S- OOK) modulation and 1 kbps data rate, for an average current consumption of 44mA

TIME-DIFFERENCE CIRCUITS: METHODOLOGY, DESIGN, AND DIGITAL REALIZATION

This thesis presents innovations for a special class of circuits called Time Difference (TD) circuits. We introduce a signal processing methodology with TD signals that alters the target signal from a magnitude perspective to time interval between two time events and systematically organizes the primary TD functions abstracted from existing TD circuits and systems. The TD circuits draw attention from a broad range of application fields. In addition, highly evolved complementary metal-oxide-semiconductor (CMOS) technology suffers from various problems related to voltage and current amplitude signal processing methods. Compared to traditional analog and digital circuits, TD circuits bring several compelling features: high-resolution, high-throughput, and low-design complexity with digital integration capability. Further, the fabrication technology is advancing into the nanometer regime; the reduction in voltage headroom limits the performance of traditional analog/mixed-signal designs. All-digital design of time-difference circuit needs to be stressed to adapt to the low-cost, low-power, and high-portability applications. We focus on Time-to-Digital Converters (TDC), one of the crucial building blocks in TD circuits. A novel algorithmic architecture is proposed based on a binary search algorithm and validated with both simulation and fabricated silicon. An all-digital structure Time-difference Amplifier (TDA) is designed and implemented to make FPGA and other all-digital implementations for TDC and related TD circuits feasible. Besides, we propose an all-digital timing measurement circuit based on the process variation from CMOS fabrication: PVTMC, which achieves a high measurement resolution: