Area/latency optimized early output asynchronous full adders and relative-timed ripple carry adders

This article presents two area/latency optimized gate level asynchronous full adder designs which correspond to early output logic. The proposed full adders are constructed using the delay-insensitive dual-rail code and adhere to the four-phase return-to-zero handshaking. For an asynchronous ripple carry adder (RCA) constructed using the proposed early output full adders, the relative-timing assumption becomes necessary and the inherent advantages of the relative-timed RCA are: (1) computation with valid inputs, i.e., forward latency is data-dependent, and (2) computation with spacer inputs involves a bare minimum constant reverse latency of just one full adder delay, thus resulting in the optimal cycle time. With respect to different 32-bit RCA implementations, and in comparison with the optimized strong-indication, weak-indication, and early output full adder designs, one of the proposed early output full adders achieves respective reductions in latency by 67.8, 12.3 and 6.1 %, while the other proposed early output full adder achieves corresponding reductions in area by 32.6, 24.6 and 6.9 %, with practically no power penalty. Further, the proposed early output full adders based asynchronous RCAs enable minimum reductions in cycle time by 83.4, 15, and 8.8 % when considering carry-propagation over the entire RCA width of 32-bits, and maximum reductions in cycle time by 97.5, 27.4, and 22.4 % for the consideration of a typical carry chain length of 4 full adder stages, when compared to the least of the cycle time estimates of various strong-indication, weak-indication, and early output asynchronous RCAs of similar size. All the asynchronous full adders and RCAs were realized using standard cells in a semi-custom design fashion based on a 32/28 nm CMOS process technology

Bibliography on Induction Motors Faults Detection and Diagnosis

International audienceThis paper provides a comprehensive list of books, workshops, conferences, and journal papers related to induction motors faults detection and diagnosis

A model for evaluating the institutional costs and benefits of ICT initiatives in teaching and learning in higher education

Significant investments are being made in the application of new information and communications technologies (ICT) to teaching and learning in higher education. However, until recently, there has been little progress in devising an integrated cost‐benefit model that decision‐makers can use to appraise ICT investment options from the wider institutional perspective. This paper describes and illustrates a model that has been developed to enable evaluations of the costs and benefits of the use of ICT. The strengths and limitations of the model are highlighted and discussed

A partial scan methodology for testing self-timed circuits

technical reportThis paper presents a partial scan method for testing control sections of macromodule based self-timed circuits for stuck-at faults. In comparison with other proposed test methods for self-timed circuits, this technique offers better fault coverage than methods using self-checking techniques, and requires fewer storage elements to be made scannable than full scan approaches with similar fault coverage. A new method is proposed to test the sequential network in this partial scan environment. Experimental data is presented to show that high fault coverage is possible using this method with only a subset of storage elements being made scannable

Compiling the language Balsa to delay insensitive hardware

A silicon compiler, Balsa-c, has been developed for the automatic synthesis of asynchronous, delay-insensitive circuits from the language Balsa. Balsa is derived from CSP with similar language constructs and a single-bit granularity type system. Balsa compiles to intermediate handshake circuits by an extended form of the com-pilation function used in the Tangram system.The handshake circuitsare subsequently mapped to CMOS implementations of 4-phase bundled-data asynchronous circuits by a suite of parameterised component-generating scripts within the Cadence design framework

DFT for fast testing of self-timed control circuits

Journal ArticleIn this paper, we present a methodology to perform fast testing of the control path of self-timed circuits [91]. The speedup is achieved by testing all the execution paths in the control simultaneously. The circuits considered in this paper are those designed using an OCCAM based circuit compiler 121. This Compiler translates an OCCAM program description into an interconnection of pre-existing self-timed macro-modules (2, 10]. The method proposed involves modifying certain modules and structures in such a way that the circuits obtained by translation using these modified modules are testable in above mentioned way

Integrating heterogeneous distributed COTS discrete-event simulation packages: An emerging standards-based approach

This paper reports on the progress made toward the emergence of standards to support the integration of heterogeneous discrete-event simulations (DESs) created in specialist support tools called commercial-off-the-shelf (COTS) discrete-event simulation packages (CSPs). The general standard for heterogeneous integration in this area has been developed from research in distributed simulation and is the IEEE 1516 standard The High Level Architecture (HLA). However, the specific needs of heterogeneous CSP integration require that the HLA is augmented by additional complementary standards. These are the suite of CSP interoperability (CSPI) standards being developed under the Simulation Interoperability Standards Organization (SISO-http://www.sisostds.org) by the CSPI Product Development Group (CSPI-PDG). The suite consists of several interoperability reference models (IRMs) that outline different integration needs of CSPI, interoperability frameworks (IFs) that define the HLA-based solution to each IRM, appropriate data exchange representations to specify the data exchanged in an IF, and benchmarks termed CSP emulators (CSPEs). This paper contributes to the development of the Type I IF that is intended to represent the HLA-based solution to the problem outlined by the Type I IRM (asynchronous entity passing) by developing the entity transfer specification (ETS) data exchange representation. The use of the ETS in an illustrative case study implemented using a prototype CSPE is shown. This case study also allows us to highlight the importance of event granularity and lookahead in the performance and development of the Type I IF, and to discuss possible methods to automate the capture of appropriate values of lookahead

ACT: A DFT tool for self-timed circuits

Journal ArticleThis paper presents a Design for Testability (DFT) tool called ACT (Asynchronous Circuit Testing) which uses a partial scan technique to make macro-module based selftimed circuits testable. The ACT tool is the first oFits kind for testing macro-module based self-timed circuits. ACT modifies designs automatically to incorporate partial scan and provides a complete path from schematic capturie to physical layout. It also has a test generation system to generate vectors for the testable design and to compute fault coverage of the generated tests. The test generatioin system includes a module for doing critical hazard free (.est generation using a new 6-valued algebra. ACT has been hilt around commercial tools from Viewlogic and Cascade. A Viewlogic schematic is used as the design entry point and Cascade tools are used for technology mapping