Design and Implementation of Parallel FIR Filter Using High Speed Vedic Multiplier

The demand for high speed processing has been increasing as a result of expanding computer and signal processing applications. Higher throughput arithmetic operations are important to achieve the desired performance in many signal processing and image processing applications. One of the key arithmetic operations in such applications is multiplication which determines the performance of the entire system. Thus the optimization of the multiplier speed and area is a challenge for many processors. This challenge has been successfully overcome by the use of ancient Vedic multiplier. This paper illustrates design and implementation of parallel Finite Impulse Response (FIR) filters using Vedic mathematics based Urdhva Tiryabhyam algorithm. The system is aiming to reduced propagation delay and area of the filter. The proposed system based on Vedic multiplier is compared with that on conventional multiplier on the basis of resources and time required for processing given data. The comparison shows the 36.29% and 15.70% reduction in propagation delay for two-parallel and three-parallel FIR filter using Vedic multiplier as compared to that of conventional multiplier. The architecture is coded in VHDL and synthesized and simulated by using Xilinx Design Suite 13.1 ISE

RECONFIGURABLE LOW POWER AND AREA EFFICIENT ESPFFIR FILTER USING VHBCSE MULTIPLIER

Reconfigurable Even Symmetric Parallel Fast Finite Impulse Response (RESPFFIR) filter shall be utilized as the Processing Element (PE) in Software Defined Radio (SDR) design to improve the throughput. The number of multipliers required in RESPFFIR filter increases when parallelism length increases. The Constant Multiplier (CM) technique is used to diminish the power consumption in FIR filters by reducing the number of Logical Operators (LO) and Logical Depth (LD). Binary Common Subexpression Elimination (BCSE) method is suitable to exploit symmetric coefficient in FIR filters. The Vertical Horizontal Binary Common Subexpression Elimination (VHBCSE) technique based Constant Multiplier (CM) design further diminish the number of LO and LD. The 2-bit BCSE algorithm has been applied vertically across neighboring coefficients and HCSE makes use of CSs that arise within each coefficient to eradicate redundant computations, which intern reduce logical operator in constant multiplier. This paper presents the design of Reconfigurable Even Symmetric Parallel Fast Finite Impulse Response (RESPFFIR) filter using VHBCSE based CM multiplier, which is reconfigurable with reduced power and area consumption without degrading the throughput. The power consumption reduces by 12% and the area required gets reduced by 24% in the proposed design when compared with existing CSE Hcub-n Multiple Constant Multiplier based  ESPFFIR filter design. The analysis is done using Cadence RC synthesize tools

Design and implementation of DA FIR filter for bio-inspired computing architecture

This paper elucidates the system construct of DA-FIR filter optimized for design of distributed arithmetic (DA) finite impulse response (FIR) filter and is based on architecture with tightly coupled co-processor based data processing units. With a series of look-up-table (LUT) accesses in order to emulate multiply and accumulate operations the constructed DA based FIR filter is implemented on FPGA. The very high speed integrated circuit hardware description language (VHDL) is used implement the proposed filter and the design is verified using simulation. This paper discusses two optimization algorithms and resulting optimizations are incorporated into LUT layer and architecture extractions. The proposed method offers an optimized design in the form of offers average miminimizations of the number of LUT, reduction in populated slices and gate minimization for DA-finite impulse response filter. This research paves a direction towards development of bio inspired computing architectures developed without logically intensive operations, obtaining the desired specifications with respect to performance, timing, and reliability

Image interpolation using Shearlet based iterative refinement

This paper proposes an image interpolation algorithm exploiting sparse representation for natural images. It involves three main steps: (a) obtaining an initial estimate of the high resolution image using linear methods like FIR filtering, (b) promoting sparsity in a selected dictionary through iterative thresholding, and (c) extracting high frequency information from the approximation to refine the initial estimate. For the sparse modeling, a shearlet dictionary is chosen to yield a multiscale directional representation. The proposed algorithm is compared to several state-of-the-art methods to assess its objective as well as subjective performance. Compared to the cubic spline interpolation method, an average PSNR gain of around 0.8 dB is observed over a dataset of 200 images

On adaptive filter structure and performance

SIGLEAvailable from British Library Document Supply Centre- DSC:D75686/87 / BLDSC - British Library Document Supply CentreGBUnited Kingdo

A review of differentiable digital signal processing for music and speech synthesis

The term “differentiable digital signal processing” describes a family of techniques in which loss function gradients are backpropagated through digital signal processors, facilitating their integration into neural networks. This article surveys the literature on differentiable audio signal processing, focusing on its use in music and speech synthesis. We catalogue applications to tasks including music performance rendering, sound matching, and voice transformation, discussing the motivations for and implications of the use of this methodology. This is accompanied by an overview of digital signal processing operations that have been implemented differentiably, which is further supported by a web book containing practical advice on differentiable synthesiser programming (https://intro2ddsp.github.io/). Finally, we highlight open challenges, including optimisation pathologies, robustness to real-world conditions, and design trade-offs, and discuss directions for future research

Volterra and general polynomial related filtering

Journal ArticleThis paper presents a review of polynomial filtering and, in particular, of tlie truncated Volterra filters. Following the introduction of the general properties of such filters, issues such as eficieiit realizations, design, adaptive algoritlims and stability are discussed