High Speed Unified Field Crypto processor for Security Applications using Verilog

Traditional cryptographic algorithms are developed on a software platform and provides information security schemes. Also, some processors have performed one of the crypto algorithms (either prime field or binary extension field) on chip level with optimal performance. The objective is to design and implement both symmetric key and public key algorithms of a cryptographic on chip level and make better architecture with pleasing performance. Crypto-processor design, have been designed with unified field instructions to make different processor architecture and improve system performance. The proposed high speed Montgomery modular multiplication and high radix Montgomery multiplication algorithms for pairing computation supports the public key algorithm. This design has been developed using Verilog HDL’s and verified using ModelSim-Altera 6.4a, and it has synthesized with Xilinx 9.1 Integrated Synthesis Environment (ISE) tool

Analysis of GF (2m) Multiplication Algorithm: Classic Method v/s Karatsuba-Ofman Multiplication Method

In recent years, finite field multiplication in GF(2m) has been widely used in various applications such as error correcting codes and cryptography. One of the motivations for fast and area efficient hardware solution for implementing the arithmetic operation of binary multiplication , in finite field GF (2m), comes from the fact, that they are the most time-consuming and frequently called operations in cryptography and other applications. So, the optimization of their hardware design is critical for overall performance of a system. Since a finite field multiplier is a crucial unit for overall performance of cryptographic systems, novel multiplier architectures, whose performances can be chosen freely, is necessary. In this paper, two Galois field multiplication algorithms (used in cryptography applications) are considered to analyze their performance with respect to parameters viz. area, power, delay, and the consequent Area×Time (AT) and Power×Delay characteristics. The objective of the analysis is to find out the most efficient GF(2m) multiplier algorithm among those considered

Low-cost, low-power FPGA implementation of ED25519 and CURVE25519 point multiplication

Twisted Edwards curves have been at the center of attention since their introduction by Bernstein et al. in 2007. The curve ED25519, used for Edwards-curve Digital Signature Algorithm (EdDSA), provides faster digital signatures than existing schemes without sacrificing security. The CURVE25519 is a Montgomery curve that is closely related to ED25519. It provides a simple, constant time, and fast point multiplication, which is used by the key exchange protocol X25519. Software implementations of EdDSA and X25519 are used in many web-based PC and Mobile applications. In this paper, we introduce a low-power, low-area FPGA implementation of the ED25519 and CURVE25519 scalar multiplication that is particularly relevant for Internet of Things (IoT) applications. The efficiency of the arithmetic modulo the prime number 2 255 − 19, in particular the modular reduction and modular multiplication, are key to the efficiency of both EdDSA and X25519. To reduce the complexity of the hardware implementation, we propose a high-radix interleaved modular multiplication algorithm. One benefit of this architecture is to avoid the use of large-integer multipliers relying on FPGA DSP modules

Entwicklung von neuen Algorithmen der Computerarithmetik in Hinsicht auf ihre Nutzung in der Kryptographie

In dieser Arbeit wird eine Reihe neuer Algorithmen aus dem Bereich der ganzzahligen Langzahlcomputerarithmetik für die Anwendungen vor allem aus dem Bereich der modernen Kryptographie entwickelt. Alle hier behandelten Verfahren wurden weiterhin in Bezug auf eine Realisierung in Hardware optimiert. Es werden drei thematische Schwerpunkte behandelt. Als erstes werden neue Methoden zur Berechnung der Modularmultiplikation aufgezeigt, die sich durch ein besonders günstiges Flächen-Zeit-Produkt auszeichnen. Das zweite Thema ist ein zeitoptimaler paralleler Algorithmus für die Modularmultiplikation, der eine Zeitkomplexität von O(log n) aufweist. Das dritte Thema behandelt ein Verfahren für die zeitoptimale Multiplikation, das eine bessere Flächen-Zeit-Komplexität als der in den meisten Prozessoren benutzte Wallace Tree und die Schönhage-Strassen-Multiplikation, welche in ihrer asymptotischen Flächen-Zeit-Komplexität besser ist als alle bisher bekannten Verfahren, aufweist