A reconfigurable frame interpolation hardware architecture for high definition video

Since Frame Rate Up-Conversion (FRC) is started to be used in recent consumer electronics products like High Definition TV, real-time and low cost implementation of FRC algorithms has become very important. Therefore, in this paper, we propose a low cost hardware architecture for realtime implementation of frame interpolation algorithms. The proposed hardware architecture is reconfigurable and it allows adaptive selection of frame interpolation algorithms for each Macroblock. The proposed hardware architecture is implemented in VHDL and mapped to a low cost Xilinx XC3SD1800A-4 FPGA device. The implementation results show that the proposed hardware can run at 101 MHz on this FPGA and consumes 32 BRAMs and 15384 slices

Learning in neuro/fuzzy analog chips

This paper focus on the design of adaptive mixed-signal fuzzy chips. These chips have parallel architecture and feature electrically-controlable surface maps. The design methodology is based on the use of composite transistors - modular and well suited for design automation. This methodology is supported by dedicated, hardware-compatible learning algorithms that combine weight-perturbation and outstar

Mapping DSP algorithms to a reconfigurable architecture Adaptive Wireless Networking (AWGN)

This report will discuss the Adaptive Wireless Networking project. The vision of the Adaptive Wireless Networking project will be given. The strategy of the project will be the implementation of multiple communication systems in dynamically reconfigurable heterogeneous hardware. An overview of a wireless LAN communication system, namely HiperLAN/2, and a Bluetooth communication system will be given. Possible implementations of these systems in a dynamically reconfigurable architecture are discussed. Suggestions for future activities in the Adaptive Wireless Networking project are also given

Three-layered perceptron that is able to learn

Впервые предложена нейросетевая архитектура и алгоритмы функционирования трехслойного перцептрона, способного дообучаться без потерь запомненной ранее информации. Новая нейронная сеть может стать альтернативой дискретным сетям адаптивной резонансной теории.Neural network architecture and algorithms of a three-layered perceptron that is able to learn without loss of previously stored information were first proposed. The new neural network can become an alternative to discrete networks of adaptive resonance theory

An adaptive detector implementation for MIMO-OFDM downlink

Cognitive radio (CR) systems require flexible and adaptive implementations of signal processing algorithms. An adaptive symbol detector is needed in the baseband receiver chain to achieve the desired flexibility of a CR system. This paper presents a novel design of an adaptive detector as an application-specific instruction-set processor (ASIP). The ASIP template is based on transport triggered architecture (TTA). The processor architecture is designed in such a manner that it can be programmed to support different suboptimal multiple-input multiple-output (MIMO) detection algorithms in a single TTA processor. The linear minimum mean-square error (LMMSE) and three variants of the selective spanning for fast enumeration (SSFE) detection algorithms are considered. The detection algorithm can be switched between the LMMSE and SSFE according to the bit error rate (BER) performance requirement in the TTA processor. The design can be scaled for different antenna configurations and different modulations. Some of the algorithm architecture co-optimization techniques used here are also presented. Unlike most other detector ASIPs, high level language is used to program the processor to meet the time-to-market requirements. The adaptive detector delivers 4.88 - 49.48 Mbps throughput at a clock frequency of 200 MHz on 90 nm technology

DISCRETE-TIME ADAPTIVE CONTROL ALGORITHMS FOR REJECTION OF SINUSOIDAL DISTURBANCES

We present new adaptive control algorithms that address the problem of rejecting sinusoids with known frequencies that act on an unknown asymptotically stable linear time-invariant system. To achieve asymptotic disturbance rejection, adaptive control algorithms of this dissertation rely on limited or no system model information. These algorithms are developed in discrete time, meaning that the control computations use sampled-data measurements. We demonstrate the effectiveness of algorithms via analysis, numerical simulations, and experimental testings. We also present extensions to these algorithms that address systems with decentralized control architecture and systems subject to disturbances with unknown frequencies