The Front end of Software-Defined Radio: Possibilities and Challenges

The use of mobile telephony has shown a spectacular\ud growth in the last 10 years. A side effect of this rapid\ud growth is an excess of mobile system standards. Therefore,\ud the Software-Defined-Radio (SDR) concept is emerging as\ud a potential pragmatic solution: it aims to build flexible radio\ud systems, which are multi-service, multi-standard, multiband,\ud re-configurable and re-programmable, by software.\ud First, this paper presents a global overview of SDR.\ud Furthermore, it discusses several front-end architectures of\ud SDR. The goal of this project is to generate knowledge about\ud designing part of the functionality of SDR, implemented by\ud rapid prototyping strategies. The focus is on the front end\ud of SDR. The technological roadmap is taken into account to\ud evaluate several architectures

Preliminary investigation of the practicality of an industrial training for engineering technology program-industries view

One of the important aspects of Engineering Technology (ET) program is the students must be able to apply a significant hands-on job throughout the program. Apart from laboratory work carried out at the university, the industrial training components can also contribute a significant practical work to enhance the skills of the students. In this study, the difference between ET and Engineering program is distinguished by proposing longer periods of industrial training in ET program. However, the effectiveness of longer periods of training must be investigated in order to find out whether this framework has to be retained for future training. For this, the university has structured the industrial training by imposing the students to undergo two (2) months training during the third (3rd) semester of year two (2), another two (2) months during the third (3rd) semester of year three (3) and finally, six (6) months during the last semester of fourth (4th) year (i.e. final semester). An interview has been conducted with two industrial panels to find out the effectiveness of the proposed training. A few suggestions and ideas given by both panels were considered for the development for industrial training syllabus in ET program

Multi-standard programmable baseband modulator for next generation wireless communication

Considerable research has taken place in recent times in the area of parameterization of software defined radio (SDR) architecture. Parameterization decreases the size of the software to be downloaded and also limits the hardware reconfiguration time. The present paper is based on the design and development of a programmable baseband modulator that perform the QPSK modulation schemes and as well as its other three commonly used variants to satisfy the requirement of several established 2G and 3G wireless communication standards. The proposed design has been shown to be capable of operating at a maximum data rate of 77 Mbps on Xilinx Virtex 2-Pro University field programmable gate array (FPGA) board. The pulse shaping root raised cosine (RRC) filter has been implemented using distributed arithmetic (DA) technique in the present work in order to reduce the computational complexity, and to achieve appropriate power reduction and enhanced throughput. The designed multiplier-less programmable 32-tap FIR-based RRC filter has been found to withstand a peak inter-symbol interference (ISI) distortion of -41 dB

Bridging ROS for Heterogeneous Integration in Mobile Robot Systems

We investigate the difficulty of integrating disparate, heterogeneous systems which have not been designed to work together. Such difficulties may arise from differences in communication protocols or data formats, making an in- tegration effort largely manual and labor intensive. The investigation is done in the context of integrating two different robot systems, one mobile platform running ROS (Robot Operating System) and one stationary two-armed ABB robot. The thesis consists of two parts. First, existing solutions to this problem (or parts of it) are examined and evaluated for their applicability. After no suitable solution is found, a tool is then created which solves the problem of integrating non-ROS compatible devices with a ROS system. The presented tool is a program that generates modular bridging nodes between ROS and other systems. Finally, the tool proves its value in the integration of two different robots, where one system also receives some additional changes for practical reasons

The fantasy of the New York nightclub : a study of an urban public space

Thesis (M.C.P.)--Massachusetts Institute of Technology, Dept. of Urban Studies and Planning, 1995.Includes bibliographical references (leaves 128-135).Joanna Elizabeth Stone.M.C.P

Optimization of DSSS Receivers Using Hardware-in-the-Loop Simulations

Over the years, there has been significant interest in defining a hardware abstraction layer to facilitate code reuse in software defined radio (SDR) applications. Designers are looking for a way to enable application software to specify a waveform, configure the platform, and control digital signal processing (DSP) functions in a hardware platform in a way that insulates it from the details of realization. This thesis presents a tool-based methodolgy for developing and optimizing a Direct Sequence Spread Spectrum (DSSS) transceiver deployed in custom hardware like Field Programmble Gate Arrays (FPGAs). The system model consists of a tranmitter which employs a quadrature phase shift keying (QPSK) modulation scheme, an additive white Gaussian noise (AWGN) channel, and a receiver whose main parts consist of an analog-to-digital converter (ADC), digital down converter (DDC), image rejection low-pass filter (LPF), carrier phase locked loop (PLL), tracking locked loop, down-sampler, spread spectrum correlators, and rectangular-to-polar converter. The design methodology is based on a new programming model for FPGAs developed in the industry by Xilinx Inc. The Xilinx System Generator for DSP software tool provides design portability and streamlines system development by enabling engineers to create and validate a system model in Xilinx FPGAs. By providing hierarchical modeling and automatic HDL code generation for programmable devices, designs can be easily verified through hardware-in-the-loop (HIL) simulations. HIL provides a significant increase in simulation speed which allows optimization of the receiver design with respect to the datapath size for different functional parts of the receiver. The parameterized datapath points used in the simulation are ADC resolution, DDC datapath size, LPF datapath size, correlator height, correlator datapath size, and rectangular-to-polar datapath size. These parameters are changed in the software enviornment and tested for bit error rate (BER) performance through real-time hardware simualtions. The final result presents a system design with minimum harware area occupancy relative to an acceptable BER degradation