837 research outputs found
Fault-Tolerant Network-on-Chip Design for Mesh-of-Tree Topology Using Particle Swarm Optimization
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Flexible Spare Core Placement in Torus Topology based NoCs and its validation on an FPGA
In the nano-scale era, Network-on-Chip (NoC) interconnection paradigm has gained importance to abide by the communication challenges in Chip Multi-Processors (CMPs). With increased integration density on CMPs, NoC components namely cores, routers, and links are susceptible to failures.
Therefore, to improve system reliability, there is a need for efficient fault-tolerant techniques that mitigate
permanent faults in NoC based CMPs. There exists several fault-tolerant techniques that address the
permanent faults in application cores while placing the spare cores onto NoC topologies. However, these
techniques are limited to Mesh topology based NoCs. There are few approaches that have realized the
fault-tolerant solutions on an FPGA, but the study on architectural aspects of NoC is limited. This paper
presents the flexible placement of spare core onto Torus topology-based NoC design by considering core
faults and validating it on an FPGA. In the first phase, a mathematical formulation based on Integer Linear
Programming (ILP) and meta-heuristic based Particle Swarm Optimization (PSO) have been proposed for the
placement of spare core. In the second phase, we have implemented NoC router addressing scheme, routing
algorithm, run-time fault injection model, and fault-tolerant placement of spare core onto Torus topology
using an FPGA. Experiments have been done by taking different multimedia and synthetic application
benchmarks. This has been done in both static and dynamic simulation environments followed by hardware
implementation. In the static simulation environment, the experimentations are carried out by scaling the
network size and router faults in the network. The results obtained from our approach outperform the
methods such as Fault-tolerant Spare Core Mapping (FSCM), Simulated Annealing (SA), and Genetic
Algorithm (GA) proposed in the literature. For the experiments carried out by scaling the network size,
our proposed methodology shows an average improvement of 18.83%, 4.55%, 12.12% in communication
cost over the approaches FSCM, SA, and GA, respectively. For the experiments carried out by scaling the
router faults in the network, our approach shows an improvement of 34.27%, 26.26%, and 30.41% over the
approaches FSCM, SA, and GA, respectively. For the dynamic simulations, our approach shows an average
improvement of 5.67%, 0.44%, and 3.69%, over the approaches FSCM, SA, and GA, respectively. In the
hardware implementation, our approach shows an average improvement of 5.38%, 7.45%, 27.10% in terms
of application runtime over the approaches SA, GA, and FSCM, respectively. This shows the superiority of
the proposed approach over the approaches presented in the literature.publishedVersio
Torus Topology based Fault-Tolerant Network-on-Chip Design with Flexible Spare Core Placement
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Network-on-Chip
Addresses the Challenges Associated with System-on-Chip Integration Network-on-Chip: The Next Generation of System-on-Chip Integration examines the current issues restricting chip-on-chip communication efficiency, and explores Network-on-chip (NoC), a promising alternative that equips designers with the capability to produce a scalable, reusable, and high-performance communication backbone by allowing for the integration of a large number of cores on a single system-on-chip (SoC). This book provides a basic overview of topics associated with NoC-based design: communication infrastructure design, communication methodology, evaluation framework, and mapping of applications onto NoC. It details the design and evaluation of different proposed NoC structures, low-power techniques, signal integrity and reliability issues, application mapping, testing, and future trends. Utilizing examples of chips that have been implemented in industry and academia, this text presents the full architectural design of components verified through implementation in industrial CAD tools. It describes NoC research and developments, incorporates theoretical proofs strengthening the analysis procedures, and includes algorithms used in NoC design and synthesis. In addition, it considers other upcoming NoC issues, such as low-power NoC design, signal integrity issues, NoC testing, reconfiguration, synthesis, and 3-D NoC design. This text comprises 12 chapters and covers: The evolution of NoC from SoC—its research and developmental challenges NoC protocols, elaborating flow control, available network topologies, routing mechanisms, fault tolerance, quality-of-service support, and the design of network interfaces The router design strategies followed in NoCs The evaluation mechanism of NoC architectures The application mapping strategies followed in NoCs Low-power design techniques specifically followed in NoCs The signal integrity and reliability issues of NoC The details of NoC testing strategies reported so far The problem of synthesizing application-specific NoCs Reconfigurable NoC design issues Direction of future research and development in the field of NoC Network-on-Chip: The Next Generation of System-on-Chip Integration covers the basic topics, technology, and future trends relevant to NoC-based design, and can be used by engineers, students, and researchers and other industry professionals interested in computer architecture, embedded systems, and parallel/distributed systems
Fault-Tolerant Application-Specific Topology based NoC and its Prototype on an FPGA
Application-Specific Networks-on-Chips (ASNoCs) are suitable communication platforms for
meeting current application requirements. Interconnection links are the primary components involved in
communication between the cores of an ASNoC design. The integration density in ASNoC increases with
continuous scaling down of the transistor size. Excessive integration density in ASNoC can result in the
formation of thermal hotspots, which can cause a system to fail permanently. As a result, fault-tolerant
techniques are required to address the permanent faults in interconnection links of an ASNoC design.
By taking into account link faults in the topology, this paper introduces a fault-tolerant application-specific
topology-based NoC design and its prototype on an FPGA. To place spare links in the ASNoC topology,
a meta-heuristic algorithm based on Particle Swarm Optimization (PSO) is proposed. By taking link
faults into account in ASNoC design, we also propose an application mapping heuristic and a table-based
fault-tolerant routing algorithm. Experiments are carried out for a specific link and any link fault in
fault-tolerant topologies generated by our approach and approaches reported in the literature. For the experimentation, we used the multi-media applications Picture-in-Picture (PiP), Moving Pictures Expert Group
(MPEG) - 4, MP3Encoder, and Video Object Plane Decoder (VOPD). Experiments are run on software
and hardware platforms. The static performance metric communication cost and the dynamic performance
metrics network latency, throughput, and router power consumption are examined using software platform.
In the hardware platform, the Field Programmable Gate Array (FPGA) is used to validate proposed
fault-tolerant topologies and analyze performance metrics such as application runtime, resource utilization,
and power consumption. The results are compared with the existing approaches, specifically Ring topology
and its modified versions on both software and hardware platforms. The experimental results obtained from
software and hardware platforms for a specific link and any link fault show significant improvements in
performance metrics using our approach when compared with the related works in the literature.publishedVersio
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