7,080 research outputs found
Metodologia Per la Caratterizzazione di amplificatori a basso rumore per UMTS
In questo lavoro si presenta una metodologia di
progettazione elettronica a livello di sistema,
affrontando il problema della caratterizzazione dello spazio di progetto dell' amplificatore a basso rumore costituente il primo stadio di un front end a conversione diretta per UMTS realizzato in tecnologia CMOS con lunghezza di canale .18u. La metodologia Ăš sviluppata al fine di valutare in modo quantititativo le specifiche ottime di sistema per il front-end stesso e si basa sul concetto di Piattaforma Analogica, che prevede la costruzione di un modello di prestazioni per il blocco analogico basato su
campionamento statistico di indici di prestazioni del blocco stesso, misurati tramite simulazione di dimensionamenti dei componenti attivi e passivi soddisfacenti un set di equazioni specifico della topologia circuitale. Gli indici di prestazioni vengono successivamente ulizzati per parametrizzare modelli comportamentali utilizzati nelle fasi di ottimizzazione a livello di sistema. Modelli comportamentali atti a rappresentare i sistemi RF sono stati pertanto studiati per ottimizzare la scelta delle metriche di prestazioni. L'ottimizzazione dei set di
equazioni atti a selezionare le configurazione di
interesse per il campionamento ha al tempo stesso richiesto l'approfondimento dei modelli di dispositivi attivi validi in tutte le regioni di funzionamento, e lo studio dettagliato della progettazione degli amplificatori a basso rumore basati su degenerazione induttiva. Inoltre,
il problema della modellizzazione a livello di sistema degli effetti della comunicazione tra LNA e Mixer Ăš stato affrontato proponendo e analizzando diverse soluzioni. Il lavoro ha permesso di condurre un'ottimizzazione del front-end UMTS, giungendo a specifiche ottime a livello di sistema per l'amplificatore stesso
Discrete-Time Chaotic-Map Truly Random Number Generators: Design, Implementation, and Variability Analysis of the Zigzag Map
In this paper, we introduce a novel discrete chaotic map named zigzag map
that demonstrates excellent chaotic behaviors and can be utilized in Truly
Random Number Generators (TRNGs). We comprehensively investigate the map and
explore its critical chaotic characteristics and parameters. We further present
two circuit implementations for the zigzag map based on the switched current
technique as well as the current-mode affine interpolation of the breakpoints.
In practice, implementation variations can deteriorate the quality of the
output sequence as a result of variation of the chaotic map parameters. In
order to quantify the impact of variations on the map performance, we model the
variations using a combination of theoretical analysis and Monte-Carlo
simulations on the circuits. We demonstrate that even in the presence of the
map variations, a TRNG based on the zigzag map passes all of the NIST 800-22
statistical randomness tests using simple post processing of the output data.Comment: To appear in Analog Integrated Circuits and Signal Processing (ALOG
Instantaneous model of a MESFET for use in linear and nonlinear circuit simulations
A formal approach for nonlinear modeling of FETs is presented. The intrinsic transistor is described by current and charge generators, that are instantaneously dependent on the two internal voltages. The extrinsic parasitic elements are also included. This instantaneous model is obtained from the small signal equivalent circuit computed at a number of bias points, by integration of the bias dependent elements. A program for using this model in nonlinear circuit analysis has been developed. The process has been carried out for two transistors, one being of low noise, and the other a power MESFET. Good agreement has been observed when comparing the nonlinear analysis with measured data. A solid-state power amplifier at 28 GHz has been designed using the power transistor, delivering 21 dBm at 1 dB compression point.Peer ReviewedPostprint (published version
Optimization of Short-Channel RF CMOS Low Noise Amplifiers by Geometric Programming
Geometric programming (GP) is an optimization method to produce globally optimal circuit parameters with high computational efficiency. Such a method has been applied to short-channel (90 nm and 180 nm) CMOS Low Noise Amplifiers (LNAs) with common-source inductive degeneration to obtain optimal design parameters by minimizing the noise figure. An extensive survey of analytical models and experimental results reported in the literature was carried out to quantify the issue of excessive thermal noise for short-channel MOSFETs. Geometric programming compatible functions have been determined to calculate the noise figure of short-channel CMOS devices by taking into consideration channel-length modulation and velocity saturation effects
Systematic Comparison of HF CMOS Transconductors
Transconductors are commonly used as active elements in high-frequency (HF) filters, amplifiers, mixers, and oscillators. This paper reviews transconductor design by focusing on the V-I kernel that determines the key transconductor properties. Based on bandwidth considerations, simple V-I kernels with few or no internal nodes are preferred. In a systematic way, virtually all simple kernels published in literature are generated. This is done in two steps: 1) basic 3-terminal transconductors are covered and 2) then five different techniques to combine two of them in a composite V-I kernel. In order to compare transconductors in a fair way, a normalized signal-to-noise ratio (NSNR) is defined. The basic V-I kernels and the five classes of composite V-I kernels are then compared, leading to insight in the key mechanisms that affect NSNR. Symbolic equations are derived to estimate NSNR, while simulations with more advanced MOSFET models verify the results. The results show a strong tradeoff between NSNR and transconductance tuning range. Resistively generated MOSFETs render the best NSNR results and are robust for future technology developments
CMOS design of chaotic oscillators using state variables: a monolithic Chua's circuit
This paper presents design considerations for monolithic implementation of piecewise-linear (PWL) dynamic systems in CMOS technology. Starting from a review of available CMOS circuit primitives and their respective merits and drawbacks, the paper proposes a synthesis approach for PWL dynamic systems, based on state-variable methods, and identifies the associated analog operators. The GmC approach, combining quasi-linear VCCS's, PWL VCCS's, and capacitors is then explored regarding the implementation of these operators. CMOS basic building blocks for the realization of the quasi-linear VCCS's and PWL VCCS's are presented and applied to design a Chua's circuit IC. The influence of GmC parasitics on the performance of dynamic PWL systems is illustrated through this example. Measured chaotic attractors from a Chua's circuit prototype are given. The prototype has been fabricated in a 2.4- mu m double-poly n-well CMOS technology, and occupies 0.35 mm/sup 2/, with a power consumption of 1.6 mW for a +or-2.5-V symmetric supply. Measurements show bifurcation toward a double-scroll Chua's attractor by changing a bias current
Analog Circuits in Ultra-Deep-Submicron CMOS
Modern and future ultra-deep-submicron (UDSM) technologies introduce several new problems in analog design. Nonlinear output conductance in combination with reduced voltage gain pose limits in linearity of (feedback) circuits. Gate-leakage mismatch exceeds conventional matching tolerances. Increasing area does not improve matching any more, except if higher power consumption is accepted or if active cancellation techniques are used. Another issue is the drop in supply voltages. Operating critical parts at higher supply voltages by exploiting combinations of thin- and thick-oxide transistors can solve this problem. Composite transistors are presented to solve this problem in a practical way. Practical rules of thumb based on measurements are derived for the above phenomena
Noise Characterization in InAlAs/InGaAs/InP pHEMTs for Low Noise Applications
In this paper, a noise revision of an InAlAs/InGaAs/InP psoeudomorphic high electron mobility transistor (pHEMT) in presented. The noise performances of the device were predicted over a range of frequencies from 1GHz to 100GHz. The minimum noise figure (NFmin), the noise resistance (Rn) and optimum source impedance (Zopt) were extracted using two approaches. A physical model that includes diffusion noise and G-R noise models and an analytical model based on an improved PRC noise model that considers the feedback capacitance Cgd. The two approaches presented matched results allowing a good prediction of the noise behaviour. The pHEMT was used to design a single stage S-band low noise amplifier (LNA). The LNA demonstrated a gain of 12.6dB with a return loss coefficient of 2.6dB at the input and greater than -7dB in the output and an overall noise figure less than 1dB
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