Analysis of power losses and Lifetime for the inverter in electric Vehicles using variable voltage Control and variable switching Frequency modified pwm

With the increasing demand for reduced emissions and improved fuel economy, the automakers are focusing on the development of electric vehicles (EVs). The performance requirements for EVs includes high driving range and long life of its components. The power converters are among the most stressed and less reliable EV drivetrain components. Hence, improving the lifetime of the power converters is essential for the success of EV adoption. The lifetime of the power converters can be improved by reducing thermal stress of the power devices, which represents the main cause of failure. Since the temperature and power losses of the power device are proportional, thermal stress can be reduced by minimizing the power losses. In addition to the lifetime improvement, minimizing the power losses of the power converters can extend the EV range since the power demand under a given loading conditions is reduced. In this regard, this thesis aims to study the impact of an existing power loss reduction technique known as variable dc-bus voltage control (VVC) on the inverter lifetime. In addition, it proposes a new pulse width modulation (PWM) strategy called variable switching frequency modified PWM (VSF-MPWM) for three-phase two level voltage source inverter. The VSF-MPWM aims to minimize the inverter power losses, but without sacrificing the output current quality. In order to study the impact of the VVC on the inverter lifetime, a lifetime estimation method is first presented. This method uses the Artemis urban and US06 driving cycles in order to obtain the thermal loading, and consequently the lifetime consumption of the inverter power devices. Then, the VSF-MPWM is proposed, which minimizes the switching loss by clamping any of the three-phase legs at the phase current peak and by reducing the number of commutations through variable switching frequency. However, in order to achieve an acceptable current quality, the proposed VSF-MPWM controls both the clamping period and the switching frequency according to the current quality constraints of the conventional PWM strategy. The impact of the VVC on the inverter lifetime and the performance of the proposed VSF-MPWM on the inverter power losses and current quality are investigated through MATLAB Simulink. The lifetime analysis reveals that the VVC has the ability to improve the lifetime of the inverter by a factor of 5.06 and 3.43 under Artemis urban and US06 driving cycles, respectively, compared to the conventional constant dc-bus voltage control (CVC). On the other hand, the simulation result shows that the proposed VSF-MPWM can save up to 35.4 % and 23.8 % of switching and power losses, respectively, compared to the conventional PWM. Meanwhile, the VSF-MPWM can obtain the same output current quality as that of the conventional PWM

A method for the suppression of fluctuations in the neutral-point potential of a three-level NPC inverter with a capacitor-voltage loop

This paper investigates the problem of fluctuation of the neutral-point potential (NPP) in a three-level NPC inverter with a capacitor-voltage loop. The phase pulse width duty cycle disturbance PWM method is proposed to suppress the NPP fluctuation efficiently. Based on the basic carrier-based Phase Disposition (PD) PWM method, the average pulse neutral-point current model is established. Then the frequency, amplitude and equivalent initial phase of the NPP fluctuation are analyzed based on the current model. According to the alternating error of the DC-link capacitor voltages, a capacitor-voltage loop with a quasi PR (proportional resonant) controller is presented. The control variable, which varies with the modulation index, phase current, load power factor, etc, can be obtained from the quasi PR controller. Finally, an experimental three-level NPC inverter is described and the validity and feasibility of the proposed method are verified by experimental results

Analytical Closed-Form Expressions for Harmonic Distortion Corresponding to Novel Switching Sequences for Neutral-Point-Clamped Inverters

Analytical closed-form expressions for harmonic distortion factors corresponding to various pulsewidth modulation (PWM) techniques for a two-level inverter have been reported in the literature. This paper derives such analytical closed-form expressions, pertaining to centered space-vector PWM (CSVPWM) and eight different advanced bus-clamping PWM (ABCPWM) schemes, for a three-level neutral-point-clamped (NPC) inverter. These ABCPWM schemes switch each phase at twice the nominal switching frequency in certain intervals of the line cycle while clamping each phase to one of the dc terminals over certain other intervals. The harmonic spectra of the output voltages, corresponding to the eight ABCPWM schemes, are studied and compared experimentally with that of CSVPWM over the entire modulation range. The measured values of weighted total harmonic distortion (WTHD) of the line voltage V-WTHD are used to validate the analytical closed-form expressions derived. The analytical expressions, pertaining to two of the ABCPWM methods, are also validated by measuring the total harmonic distortion (THD) in the line current I-THD on a 2.2-kW constant volts-per-hertz induction motor drive