Design and analysis of memristor-based reliable crossbar architectures

The conventional transistor-based computing landscape is already undergoing dramatic changes. While transistor-based devices’ scaling is approaching its physical limits in nanometer technologies, memristive technologies hold the potential to scale to much smaller geometries. Memristive devices are used majorly in memory design but they also have unignorable applications in logic design, neuromorphic computing, sensors among many others. The most critical research and development problems that must be resolved before memristive architectures become mainstream are related to their reliability. One of such reliability issue is the sneak-paths current which limits the maximum crossbar array size. This thesis presents various designs of the memristor based crossbar architecture and corresponding experimental analysis towards addressing its reliability issues. Novel contribution of this thesis starts with the formulation of robust analytic models for read and write schemes used in memristive crossbar arrays. These novel models are less restrictive and are suitable for accurate mathematical analysis of any mn crossbar array and the evaluation of their performance during these critical operations. In order to minimise the sneak-paths problem, we propose techniques and conditions for reliable read operations using simultaneous access of multiple bits in the crossbar array. Two new write techniques are also presented, one to minimise failure during single cell write and the other designed for multiple cells write operation. Experimental results prove that the single write technique minimises write voltage drop degradation compared to existing techniques. Test results from the multiple cells write technique show it consumes less power than other techniques depending on the chosen configuration. Lastly, a novel Verilog-A memristor model for simulation and analysis of memristor’s application in gas sensing is presented. This proposed model captures the gas sensing properties of titanium-dioxide using gas concentration to control the overall memristance of the device. This model is used to design and simulate a first-of-its-kind sneak-paths free memristor-based gas detection arrays. Experimental results from a 88 memristor sensor array show that there is a ten fold improvement in the accuracy of the sensor’s response when compared with a single memristor sensor

Device Modeling and Circuit Design of Neuromorphic Memory Structures

The downscaling of CMOS technology and the benefits gleaned thereof have made it the cornerstone of the semiconductor industry for many years. As the technology reaches its fundamental physical limits, however, CMOS is expected to run out of steam instigating the exploration of new nanoelectronic devices. Memristors have emerged as promising candidates for future computing paradigms, specifically, memory arrays and neuromorphic circuits. Towards this end, this dissertation will explore the use of two memristive devices, namely, Transition Metal Oxide (TMO) devices and Insulator Metal Transition (IMT) devices in constructing neuromorphic circuits. A compact model for TMO devices is first proposed and verified against experimental data. The proposed model, unlike most of the other models present in the literature, leverages the instantaneous resistance of the device as the state variable which facilitates parameter extraction. In addition, a model for the forming voltage of TMO devices is developed and verified against experimental data and Monte Carlo simulations. Impact of the device geometry and material characteristics of the TMO device on the forming voltage is investigated and techniques for reducing the forming voltage are proposed. The use of TMOs in syanptic arrays is then explored and a multi-driver write scheme is proposed that improves their performance. The proposed technique enhances voltage delivery across the selected cells via suppressing the effective line resistance and leakage current paths, thus, improving the performance of the crossbar array. An IMT compact model is also developed and verified against experiemntal data and electro-thermal device simulations. The proposed model describes the device as a memristive system with the temperature being the state variable, thus, capturing the temperature dependent resistive switching of the IMT device in a compact form suitable for SPICE implementation. An IMT based Integrate-And-Fire neuron is then proposed. The IMT neuron leverages the temperature dynamics of the device to deliver the functionality of the neuron. The proposed IMT neuron is more compact than its CMOS counterparts as it alleviates the need for complex CMOS circuitry. Impact of the IMT device parameters on the neuron\u27s performance is then studied and design considerations are provided

Neuro-memristive Circuits for Edge Computing: A review

The volume, veracity, variability, and velocity of data produced from the ever-increasing network of sensors connected to Internet pose challenges for power management, scalability, and sustainability of cloud computing infrastructure. Increasing the data processing capability of edge computing devices at lower power requirements can reduce several overheads for cloud computing solutions. This paper provides the review of neuromorphic CMOS-memristive architectures that can be integrated into edge computing devices. We discuss why the neuromorphic architectures are useful for edge devices and show the advantages, drawbacks and open problems in the field of neuro-memristive circuits for edge computing

Efficient Memristive Stochastic Differential Equation Solver

Herein, an efficient numerical solver for stochastic differential equations based on memristors is presented. The solver utilizes the stochastic switching effect in memristive devices to simulate the generation of a Brownian path and employs iterative Euler method computations within memristive crossbars. The correctness of the solution paths generated by the system is examined by solving the Black–Scholes equations and comparing the paths to analytical solutions. It is found that the absolute error of a 128-step path is limited to an order of (Figure presented.). The tolerance of the system to crossbar nonidealities is also assessed by comparing the numerical and analytical paths' variation in error. The numerical solver is sensitive to the variation in operating conditions, with the error increasing by (Figure presented.), (Figure presented.), and (Figure presented.) as the ambient temperature, wire resistance, and stuck probability of the memristor increase to extreme conditions. The solver is tested on a variety of problems to show its utility for different calculations. And, the resource consumption of the proposed structure built with existing technology is estimated and it is compared with similar iterative solvers. The solver generates a solution with the same level of accuracy from (Figure presented.) to (Figure presented.) faster than similar digital or mixed-signal designs

Applications of Computation-In-Memory Architectures based on Memristive Devices

Today's computing architectures and device technologies are unable to meet the increasingly stringent demands on energy and performance posed by emerging applications. Therefore, alternative computing architectures are being explored that leverage novel post-CMOS device technologies. One of these is a Computation-in-Memory architecture based on memristive devices. This paper describes the concept of such an architecture and shows different applications that could significantly benefit from it. For each application, the algorithm, the architecture, the primitive operations, and the potential benefits are presented. The applications cover the domains of data analytics, signal processing, and machine learning

Controlling Ionic Transport in RRAM for Memory and Neuromorphic Computing Applications

Resistive random-access memory, based on a simple two-terminal device structure, has attracted tremendous interest recently for applications ranging from non-volatile data storage to neuromorphic computing. Resistive switching (RS) effects in RRAM devices originate from internal, microscopic ionic migration and the associated electrochemical processes which modify the materials’ chemical composition and subsequently their electrical and other physical properties. Therefore, controlling the internal ionic transport and redox reaction processes, ideally at the atomic scale, is necessary to optimize the device performance for practical applications with large-size arrays. In this thesis we present our efforts in understanding and controlling the ionic processes in RRAM devices. This thesis presents a comprehensive study on the fundamental understanding on physical mechanism of the ionic processes and the optimization of materials and device structures to achieve desirable device performance based on theoretical calculations and experimental engineering. First, I investigate the electronic structure of Ta2O5 polymorphs, a resistive switching material, and the formation and interaction of oxygen vacancies in amorphous Ta2O5, an important mobile defect responsible for the resistive switching process, using first-principles calculations. Based on the understanding of the fundamental properties of the switching material and the defect, we perform detailed theoretical and experimental analyses that reveal the dynamic vacancy charge transition processes, further helping the design and optimization of the oxide-based RRAM devices. Next, we develop a novel structure including engineered nanoporous graphene to control the internal ionic transport and redox reaction processes at the atomic level, leading to improved device performance. We demonstrate that the RS characteristics can be systematically tuned by inserting a graphene layer with engineered nanopores at a vacancy-exchange interface. The amount of vacancies injected in the switching layer and the size of the conducting filaments can be effectively controlled by the graphene layer working as an atomically-thin ion-blocking material in which ionic transports/reactions are allowed only through the engineered nanosized openings. Lastly, better incremental switching characteristics with improved linearity are obtained through optimization of the switching material density. These improvements allow us to build RRAM crossbar networks for data clustering analysis through unsupervised, online learning in both neuromorphic applications and arithmetic applications in which accurate vector-matrix multiplications are required. We expect the optimization approaches and the optimized devices can be used in other machine learning and arithmetic computing systems, and broaden the range of problems RRAM based network can solve.PHDMaterials Science and EngineeringUniversity of Michigan, Horace H. Rackham School of Graduate Studieshttps://deepblue.lib.umich.edu/bitstream/2027.42/146119/1/jihang_1.pd

Improving Performance and Endurance for Crossbar Resistive Memory

Resistive Memory (ReRAM) has emerged as a promising non-volatile memory technology that may replace a significant portion of DRAM in future computer systems. When adopting crossbar architecture, ReRAM cell can achieve the smallest theoretical size in fabrication, ideally for constructing dense memory with large capacity. However, crossbar cell structure suffers from severe performance and endurance degradations, which come from large voltage drops on long wires. In this dissertation, I first study the correlation between the ReRAM cell switching latency and the number of cells in low resistant state (LRS) along bitlines, and propose to dynamically speed up write operations based on bitline data patterns. By leveraging the intrinsic in-memory processing capability of ReRAM crossbars, a low overhead runtime profiler that effectively tracks the data patterns in different bitlines is proposed. To achieve further write latency reduction, data compression and row address dependent memory data layout are employed to reduce the numbers of LRS cells on bitlines. Moreover, two optimization techniques are presented to mitigate energy overhead brought by bitline data patterns tracking. Second, I propose XWL, a novel table-based wear leveling scheme for ReRAM crossbars and study the correlation between write endurance and voltage stress in ReRAM crossbars. By estimating and tracking the effective write stress to different rows at runtime, XWL chooses the ones that are stressed the most to mitigate. Additionally, two extended scenarios are further examined for the performance and endurance issues in neural network accelerators as well as 3D vertical ReRAM (3D-VRAM) arrays. For the ReRAM crossbar-based accelerators, by exploiting the wearing out mechanism of ReRAM cell, a novel comprehensive framework, ReNEW, is proposed to enhance the lifetime of the ReRAM crossbar-based accelerators, particularly for neural network training. To reduce the write latency in 3D-VRAM arrays, a collection of techniques, including an in-memory data encoding scheme, a data pattern estimator for assessing cell resistance distributions, and a write time reduction scheme that opportunistically reduces RESET latency with runtime data patterns, are devised

Minimising impact of wire resistance in low-power crossbar array write scheme

This paper presents a circuit level analysis of write operation in memristor crossbar memory array with and without line resistance. Three write schemes: floating line, V/2 and V/3 are investigated. Analysis shows that floating line scheme could also be considered reliable in arrays with aspect ratio of 1:1 and negligible line resistance just like the latter two schemes. Further analysis also shows that high density crossbar structures cannot be designed using any of the three schemes with worst case line resistance and data distribution within the array. To solve this problem, we propose a voltage compensating technique for write voltage degradation caused by line resistance during write operation on crossbar array. This technique is able to enhance write voltage in the presence of worst case line resistance and thus enable the design of higher density and reliable crossbar array