Circuit theoretical methods for efficient solution of finite element structural mechanics problems

Ankara : The Department of Electrical and Electronics Engineering and the Institute of Engineering and Sciences of Bilkent Univ., 1999.Thesis (Ph.D.) -- Bilkent University, 1999.Includes bibliographical references leaves 78-84.Shrinking device dimensions in integrated circuit technology made integrated circuits with millions of components a reality. As a result of this advance, electrical circuit simulators that can handle very large number of components have emerged. These programs use new circuit simulation techniques which approximate the system with reduced order models, and can find solutions accurately and quickly. This study proposes formulating the structural mechanics problems using FEM, and then employing the recent speedup techniques used in circuit simulation. This is obtained by generating an equivalent resistor-inductor-capacitor circuit containing controlled sources. We analyze the circuits with general-purpose circuit simulation programs, HSPICE, and an in-house developed circuit simulation program, MAWE, which makes use of generalized asymptotic waveform evaluation (AWE) technique. AWE is a moment matching technique that has been successfully used in circuit simulation for solutions of large sets of equations. Several examples on the analysis of the displacement distributions in rigid bodies have shown that using circuit simulators instead of conventional FEM solution methods improves simulation speed without a significant loss of accuracy. Pole analysis via congruence transformations (PACT) technique is a recent algorithm used for obtaining lower order models for large circuits. For a further reduction in time, we employed a similar algorithm in structural mechanics problems before obtaining the equivalent circuit. The results are very promising.Ekinci, Ahmet SuatPh.D

PLAWE: A piecewise linear circuit simulator using asymptotic waveform evaluation

Ankara : Department of Electrical and Electronics Engineering and the Institute of Engineering and Science of Bilkent University, 1994.Thesis (Ph.D.) -- Bilkent University, 1994.Includes bibliographical references leaves 73-81.A new circuit simulation program, PLAWE, is developed for the transient analysis of VLSI circuits. PLAWE uses Asymptotic Waveform Evaluation (AWE) technique, which is a new method to analyze linear(ized) circuits, and Piecewise Linear (PWL) approach for DC representation of nonlinear elements. AWE employs a form of Pade approximation rather than numerical integration techniques to approximate the response of linear(ized) circuits in either the time or the frequency domain. AWE is typically two or three orders of magnitude faster than traditional simulators in analyzing large linear circuits. However, it can handle only linear(ized) circuits, while the transient analysis problem is generally nonlinear due to the presence of nonlinear devices such as diodes, transistors, etc.. We have applied the AWE technique to the transient simulation of nonlinear circuits by using static PWL models for nonlinear elements. But, finding a good static PWL model which fits well to the actual i — v characteristics of a nonlinear device is not an easy task and in addition, static PWL modelling results in low accuracy. Therefore, we have developed a dynamic PWL modeling technique which uses SPICE models for nonlinear elements to enhance the accuracy of the simulation while preserving the efficiency gain obtained with AWE. Hence, there is no modelling problem and we can adjust the accuracy level by varying some parameters. If the required level of accuracy is increased, more simulation time is needed. Practical examples are given to illustrate the significant improvement in accuracy. For circuits containing especially weakly nonlinear devices, this method is typically at least one order of magnitude faster than HSPICE. A fast and convergent iteration method for piecewise-linear analysis of nonlinear resistive circuits is presented. Most of the existing algorithms are applicable only to a limited class of circuits. In general, they are either not convergent or too slow for large circuits. The new algorithm presented in this thesis is much more efficient than the existing ones and can be applied to any piecewise-linear circuit. It is based on the piecewise-linear version of the Newton-Raphson algorithm. As opposed to the NewtonRaphson method, the new algorithm is globally convergent from an arbitrary starting point. It is simple to understand and it can be easily programmed. Some numerical examples are given in order to demonstrate the effectiveness of the presented algorithm in terms of the amount of computation.Topçu, SatılmışPh.D

Analysis of High-Speed VLSI Interconnects Using the Asymptotic Waveform Evaluation Technique

The common methods for interconnect delay estimation rely upon an RC tree model. These methods are not adequate for high-speed or printed circuit board applications where more elaborate interconnect models are required. The models in this case may contain general RLC lumped and distributed networks. The recently published asymptotic waveform evaluation (AWE) technique provides a generalized approach to lumped RLC circuit response approximations. In addition, more accurate results compared with the RC tree methods can be obtained at an incremental cost in CPU time. However, with higher signal speeds, the electrical lengths of interconnects can become a significant fraction of a wavelength. Consequently, the conventional lumped-impedance interconnect model is not adequate in this case. Two new results are described in this paper: 1) Generalization of the AWE method to handle interconnect models which contain distributed elements. 2) Application of the generalized AWE technique to the important case where the distributed elements can be modeled as lossy coupled transmission lines. The generalized AWE technique is useful for both delay and crosstalk estimation and can be used to evaluate transient responses of high-speed interconnect circuits with negligible error compared with conventional circuit simulators such as SPICE while being two to three orders of magnitude faster

Model order reduction techniques for circuit simulation

Thesis (Ph. D.)--Massachusetts Institute of Technology, Dept. of Electrical Engineering and Computer Science, 1994.Includes bibliographical references.by ?Luís Miguel Silveira.Ph.D

Model order reduction techniques for circuit simulation

Includes bibliographical references (p. 156-160).Supported in part by the Semiconductor Research Corporation. SRC 93-SJ-558 Supported in part by the National Science Foundation / Advanced Research Projects Agency. MIP 91-17724Luis Miguel Silveira