A system to detect timing problems in digital circuits

Nowadays, the digital circuit production is carried out specifying the circuit functionality using a hardware description language. Then, this specification is synthesized down to a structural netlist suitable for use by the target technologys place-and-route applications. Many synthesis tools make this task introducing some unnecessary gates and wires in the final circuit. As a consequence, it can appear a circuit containing one or more paths that do not influence the circuit output. This kind of non-relevant paths is known as False Path. The problem with false paths is that if they are not considered, the circuit delay may be overestimated during design analysis and optimization. For this reason, the digital circuit industry is looking for effective methods and tools to overcome the mentioned drawbacks. This paper presents a system to detect False Paths based on the analysis of the circuit intermediate specification. The tool analyzes the specification using compilation techniques and then applies some special purpose algorithms for detecting false paths. Furthermore, it shows the gates and wires that are not necessary for the circuit final version.Presentado en el VII Workshop Ingeniería de Software (WIS)Red de Universidades con Carreras en Informática (RedUNCI

A system to detect timing problems in digital circuits

Nowadays, the digital circuit production is carried out specifying the circuit functionality using a hardware description language. Then, this specification is synthesized down to a structural netlist suitable for use by the target technologys place-and-route applications. Many synthesis tools make this task introducing some unnecessary gates and wires in the final circuit. As a consequence, it can appear a circuit containing one or more paths that do not influence the circuit output. This kind of non-relevant paths is known as False Path. The problem with false paths is that if they are not considered, the circuit delay may be overestimated during design analysis and optimization. For this reason, the digital circuit industry is looking for effective methods and tools to overcome the mentioned drawbacks. This paper presents a system to detect False Paths based on the analysis of the circuit intermediate specification. The tool analyzes the specification using compilation techniques and then applies some special purpose algorithms for detecting false paths. Furthermore, it shows the gates and wires that are not necessary for the circuit final version.Presentado en el VII Workshop Ingeniería de Software (WIS)Red de Universidades con Carreras en Informática (RedUNCI

The 1974 NASA-ASEE summer faculty fellowship aeronautics and space research program

Research activities by participants in the fellowship program are documented, and include such topics as: (1) multispectral imagery for detecting southern pine beetle infestations; (2) trajectory optimization techniques for low thrust vehicles; (3) concentration characteristics of a fresnel solar strip reflection concentrator; (4) calaboration and reduction of video camera data; (5) fracture mechanics of Cer-Vit glass-ceramic; (6) space shuttle external propellant tank prelaunch heat transfer; (7) holographic interferometric fringes; and (8) atmospheric wind and stress profiles in a two-dimensional internal boundary layer

Waiting False Path Analysis of Sequential Logic Circuits for Performance Optimization

This paper introduces a new class of false path, which is sensitizable but does not affect the decision of the clock period. We call such false paths waiting false paths, which correspond to multi-cycle operations controlled by wait states. The allowable delay time of waiting false paths is greater than the clock period. When the number of allowable clock cycles for each path is determined, the delay of the path can be the product of the clock period and the allowable cycles. This paper presents a method to analyze allowable cycles and to detect waiting false paths based on symbolic traversal of FSM. We have applied our method to 30 ISCAS89 FSM benchmarks and found that 22 circuits include such paths. 11 circuits among them include such paths which are critical paths, where the delay is measured as the number of gates on the path. Informations on such paths can be used in the logic synthesis to reduce the number of gates and in the layout synthesis to reduce the size of gates. 1 Intro..

An Algorithm for Incremental Timing Analysis

In recent years, many new algorithms have been proposed for performing a complete timing analysis of sequential logic circuits. In this paper, we present an incremental timing analysis algorithm. When an incremental design change is made on the logic network, this algorithm will identify the portion of design for which the timing is affected, and quickly derive the new arrival times and slacks. A fast incremental timing analysis is desirable for users doing interactive logic design. It is particularly important for a logic synthesis program, which needs to evaluate the circuit delays under many logic modifications