Testing for delay defects utilizing test data compression techniques

textAs technology shrinks new types of defects are being discovered and new fault models are being created for those defects. Transition delay and path delay fault models are two such models that have been created, but they still fall short in that they are unable to obtain a high test coverage of smaller delay defects; these defects can cause functional behavior to fail and also indicate potential reliability issues. The first part of this dissertation addresses these problems by presenting an enhanced timing-based delay fault testing technique that incorporates the use of standard delay ATPG, along with timing information gathered from standard static timing analysis. Utilizing delay fault patterns typically increases the test data volume by 3-5X when compared to stuck-at patterns. Combined with the increase in test data volume associated with the increase in gate count that typically accompanies the miniaturization of technology, this adds up to a very large increase in test data volume that directly affect test time and thus the manufacturing cost. The second part of this dissertation presents a technique for improving test compression and reducing test data volume by using multiple expansion ratios while determining the configuration of the scan chains for each of the expansion ratios using a dependency analysis procedure that accounts for structural dependencies as well as free variable dependencies to improve the probability of detecting faults. Finally, this dissertation addresses the problem of unknown values (X’s) in the output response data corrupting the data and degrading the performance of the output response compactor and thus the overall amount of test compression. Four techniques are presented that focus on handling response data with large percentages of X’s. The first uses X-canceling MISR architecture that is based on deterministically observing scan cells, and the second is a hybrid approach that combines a simple X-masking scheme with the X-canceling MISR for further gains in test compression. The third and fourth techniques revolve around reiterative LFSR X-masking, which take advantage of LFSR-encoded masks that can be reused for multiple scan slices in novel ways.Electrical and Computer Engineerin

Optimal Unknown Bit Filtering for Test Response Masking

[[abstract]]In this paper presents a new X-Masking scheme for response compaction. It filters all X states from test response that can no unknown value input to response compactor. In the experimental results, this scheme increased less control data and maintain same observability.[[conferencedate]]20121104~20121107[[iscallforpapers]]Y[[conferencelocation]]New Taipei, Taiwa

Silicon compilation

Silicon compilation is a term used for many different purposes. In this paper we define silicon compilation as a mapping from some higher level description into layout. We define the basic issues in structural and behavioral silicon compilation and some possible solutions to those issues. Finally, we define the concept of an intelligent silicon compiler in which the compiler evaluates the quality of the generated design and attempts to improve it if it is not satisfactory

Pseudo-functional testing: bridging the gap between manufacturing test and functional operation.

Yuan, Feng.Thesis (M.Phil.)--Chinese University of Hong Kong, 2009.Includes bibliographical references (leaves 60-65).Abstract also in Chinese.Abstract --- p.iAcknowledgement --- p.iiChapter 1 --- Introduction --- p.1Chapter 1.1 --- Manufacturing Test --- p.1Chapter 1.1.1 --- Functional Testing vs. Structural Testing --- p.2Chapter 1.1.2 --- Fault Model --- p.3Chapter 1.1.3 --- Automatic Test Pattern Generation --- p.4Chapter 1.1.4 --- Design for Testability --- p.6Chapter 1.2 --- Pseudo-Functional Manufacturing Test --- p.13Chapter 1.3 --- Thesis Motivation and Organization --- p.16Chapter 2 --- On Systematic Illegal State Identification --- p.19Chapter 2.1 --- Introduction --- p.19Chapter 2.2 --- Preliminaries and Motivation --- p.20Chapter 2.3 --- What is the Root Cause of Illegal States? --- p.22Chapter 2.4 --- Illegal State Identification Flow --- p.26Chapter 2.5 --- Justification Scheme Construction --- p.30Chapter 2.6 --- Experimental Results --- p.34Chapter 2.7 --- Conclusion --- p.35Chapter 3 --- Compression-Aware Pseudo-Functional Testing --- p.36Chapter 3.1 --- Introduction --- p.36Chapter 3.2 --- Motivation --- p.38Chapter 3.3 --- Proposed Methodology --- p.40Chapter 3.4 --- Pattern Generation in Compression-Aware Pseudo-Functional Testing --- p.42Chapter 3.4.1 --- Circuit Pre-Processing --- p.42Chapter 3.4.2 --- Pseudo-Functional Random Pattern Generation with Multi-Launch Cycles --- p.43Chapter 3.4.3 --- Compressible Test Pattern Generation for Pseudo-Functional Testing --- p.45Chapter 3.5 --- Experimental Results --- p.52Chapter 3.5.1 --- Experimental Setup --- p.52Chapter 3.5.2 --- Results and Discussion --- p.54Chapter 3.6 --- Conclusion --- p.56Chapter 4 --- Conclusion and Future Work --- p.58Bibliography --- p.6

A design by example Regular Structure Generator

Originally presented as author's thesis (M.S.--Massachusetts Institute of Technology), 1985.Bibliography: leaves 108-111.Supported in part by the U.S. Air Force Office of Scientific Research contract F49620-84-C-0004Cyrus S. Bamji

FuncTeller: How Well Does eFPGA Hide Functionality?

Hardware intellectual property (IP) piracy is an emerging threat to the global supply chain. Correspondingly, various countermeasures aim to protect hardware IPs, such as logic locking, camouflaging, and split manufacturing. However, these countermeasures cannot always guarantee IP security. A malicious attacker can access the layout/netlist of the hardware IP protected by these countermeasures and further retrieve the design. To eliminate/bypass these vulnerabilities, a recent approach redacts the design's IP to an embedded field-programmable gate array (eFPGA), disabling the attacker's access to the layout/netlist. eFPGAs can be programmed with arbitrary functionality. Without the bitstream, the attacker cannot recover the functionality of the protected IP. Consequently, state-of-the-art attacks are inapplicable to pirate the redacted hardware IP. In this paper, we challenge the assumed security of eFPGA-based redaction. We present an attack to retrieve the hardware IP with only black-box access to a programmed eFPGA. We observe the effect of modern electronic design automation (EDA) tools on practical hardware circuits and leverage the observation to guide our attack. Thus, our proposed method FuncTeller selects minterms to query, recovering the circuit function within a reasonable time. We demonstrate the effectiveness and efficiency of FuncTeller on multiple circuits, including academic benchmark circuits, Stanford MIPS processor, IBEX processor, Common Evaluation Platform GPS, and Cybersecurity Awareness Worldwide competition circuits. Our results show that FuncTeller achieves an average accuracy greater than 85% over these tested circuits retrieving the design's functionality.Comment: To be published in the proceedings of the 32st USENIX Security Symposium, 202