Design of a 4GHz programmable frequency synthesizer for IEEE-802.11a standards

Frequency synthesizer is one of the most versatile component and heart of any system. It is used to correct the phase & frequency error so that the signal coming from the different part of the circuit or from the wireless medium does not cause any attenuation or distortion due to frequency dependent or phase dependent error. Present days the Frequency Synthesizer is also used for the wireless communication in the GHz range to correct the phase and frequency error as well as provide synchronization with low locking time, reduced skew and jitter. The frequency synthesizer is used inside a processor to provide the clock synchronization, clock recovery. Due to all above important application in the Analog and mixed signal as well as in digital signal analysis there is a necessity of a Frequency synthesizer with higher Capture range low lock time and with a low settling time. The design of given Frequency synthesizer is done in the 90nm (GPDK 090) process technology in CADANCE virtuoso Analog design environment. To detect the phase and frequency error for any unsymmetrical pulse the voltage based phase frequency detector is used in the design. Voltage controlled oscillator is also a very important part which decide the range of frequency synthesizer. The VCO used here is a current starved Ring oscillator which consumes a very low power. The loop filter is an important component that decides the Dynamic response of the frequency synthesizer. The rise time damping ratio, settling time, bandwidth and output signal to noise ratio of the circuit. The loop filter used here is a passive lead lag filter which is designed with the resistor and capacitor. The layout of the frequency synthesizer is done in the CADANCE virtuoso XL layout editor and different type of simulation is done in the spectre simulator. The power consumed in the frequency synthesizer is 0.22091 m watt at 1.2 V supply voltage and the lock time is 220 ns. The divider is a very important part which made the frequency synthesizer circuit tuneable in a wide range of input frequency so for this purpose we designed it programmable which divide in N/N+1 ratio

Design and Analysis of an Efficient Phase Locked Loop for Fast Phase and Frequency Acquisition

The most versatile application of the phase locked loops (PLL) is for clock generation and clock recovery in microprocessor, networking, communication systems, and frequency synthesizers. Phase locked-loops (PLLs) are commonly used to generate well-timed on-chip clocks in high-performance digital systems. Modern wireless communication systems employ Phase Locked Loop (PLL) mainly for synchronization, clock synthesis, skew and jitter reduction. Because of the increase in the speed of the circuit operation, there is a need of a PLL circuit with faster locking ability. Many present communication systems operate in the GHz frequency range. Hence there is a necessity of a PLL which must operate in the GHz range with less lock time. PLL is a mixed signal circuit as its architecture involves both digital and analog signal processing units. The present work focuses on the redesign of a PLL system using the 90 nm process technology (GPDK090 library) in CADENCE Virtuoso Analog Design Environment. Here a current starved ring oscillator has been considered for its superior performance in form of its low chip area, low power consumption and wide tuneable frequency range. The layout structure of the PLL is drawn in CADENCE VirtuosoXL Layout editor. Different types of simulations are carried out in the Spectre simulator. The pre and post layout simulation results of PLL are reported in this work. It is found that the designed PLL consumes 11.68mW power from a 1.8V D.C. supply and have a lock time 280.6 ns. As the voltage controlled oscillator (VCO) is the heart of the PLL, so the optimization of the VCO circuit is also carried out using the convex optimization technique. The results of the VCO designed using the convex optimization method is compared with traditional method

저 잡음 디지털 위상동기루프의 합성

학위논문 (박사)-- 서울대학교 대학원 : 전기·컴퓨터공학부, 2014. 2. 정덕균.As a device scaling proceeds, Charge Pump PLL has been confronted by many design challenges. Especially, a leakage current in loop filter and reduced dynamic range due to a lower operating voltage make it difficult to adopt a conventional analog PLL architecture for a highly scaled technology. To solve these issues, All Digital PLL (ADPLL) has been widely studied recently. ADPLL mitigates a filter leakage and a reduced dynamic range issues by replacing the analog circuits with digital ones. However, it is still difficult to get a low jitter under low supply voltage. In this thesis, we propose a dual loop architecture to achieve a low jitter even with a low supply voltage. And bottom-up based multi-step TDC and DCO are proposed to meet both fine resolution and wide operation range. In the aspect of design methodology, ADPLL has relied on a full custom design method although ADPLL is fully described in HDL (Hardware Description Language). We propose a new cell based layout technique to automatically synthesize the whole circuit and layout. The test chip has no linearity degradation although it is fully synthesized using a commercially available auto P&R tool. We has implemented an all digital pixel clock generator using the proposed dual loop architecture and the cell based layout technique. The entire circuit is automatically synthesized using 28nm CMOS technology. And s-domain linear model is utilized to optimize the jitter of the dual-loop PLL. Test chip occupies 0.032mm2, and achieves a 15ps_rms integrated jitter although it has extremely low input reference clock of 100 kHz. The whole circuit operates at 1.0V and consumes only 3.1mW.Abstract i Lists of Figures vii Lists of Tables xiii 1. Introduction 1 1.1 Thesis Motivation and Organization 1 1.1.1 Motivation 1 1.1.2 Thesis Organization 2 1.2 PLL Design Issues in Scaled CMOS Technology 3 1.2.1 Low Supply Voltage 4 1.2.2 High Leakage Current 6 1.2.3 Device Reliability: NBTI, HCI, TDDB, EM 8 1.2.4 Mismatch due to Proximity Effects: WPE, STI 11 1.3 Overview of Clock Synthesizers 14 1.3.1 Dual Voltage Charge Pump PLL 14 1.3.2 DLL Based Edge Combining Clock Multiplier 16 1.3.3 Recirculation DLL 17 1.3.4 Reference Injected PLL 18 1.3.5 All Digital PLL 19 1.3.6 Flying Adder Clock Synthesizer 20 1.3.7 Dual Loop Hybrid PLL 21 1.3.8 Comparisons 23 2. Tutorial of ADPLL Design 25 2.1 Introduction 25 2.1.1 Motivation for a pure digital 25 2.1.2 Conversion to digital domain 26 2.2 Functional Blocks 26 2.2.1 TDC, and PFD/Charge Pump 26 2.2.2 Digital Loop Filter and Analog R/C Loop Filter 29 2.2.3 DCO and VCO 34 2.2.4 S-domain Model of the Whole Loop 34 2.2.5 ADPLL Loop Design Flow 36 2.3 S-domain Noise Model 41 2.3.1 Noise Transfer Functions 41 2.3.2 Quantization Noise due to Limited TDC Resolution 45 2.3.3 Quantization Noise due to Divider ΔΣ Noise 46 2.3.4 Quantization Noise due to Limited DCO Resolution 47 2.3.5 Quantization Noise due to DCO ΔΣ Dithering 48 2.3.6 Random Noise of DCO and Input Clock 50 2.3.7 Over-all Phase Noise 50 3. Synthesizable All Digital Pixel Clock PLL Design 53 3.1 Overview 53 3.1.1 Introduction of Pixel Clock PLL 53 3.1.1 Design Specifications 55 3.2 Proposed Architecture 60 3.2.1 All Digital Dual Loop PLL 60 3.2.2 2-step controlled TDC 61 3.2.3 3-step controlled DCO 64 3.2.4 Digital Loop Filter 76 3.3 S-domain Noise Model 78 3.4 Loop Parameter Optimization Based on the s-domain Model 85 3.5 RTL and Gate Level Circuit Design 88 3.5.1 Overview of the design flow 88 3.5.2 Behavioral Simulation and Gate level synthesis 89 3.5.1 Preventing a meta-stability 90 3.5.1 Reusable Coding Style 92 3.6 Layout Synthesis 94 3.6.1 Auto P&R 94 3.6.2 Design of Unit Cells 97 3.6.3 Linearity Degradation in Synthesized TDC 98 3.6.4 Linearity Degradation in Synthesized DCO 106 3.7 Experiment Results 109 3.7.1 DCO measurement 109 3.7.2 PLL measurement 113 3.8 Conclusions 117 A. Device Technology Scaling Trends 118 A.1. Motivation for Technology Scaling 118 A.2. Constant Field Scaling 120 A.3. Quasi Constant Voltage Scaling 123 A.4. Device Technology Trends in Real World 124 B. Spice Simulation Tip for a DCO 137 C. Phase Noise to Jitter Conversion 141 Bibliography 144 초록 151Docto