Stall Pattern Avoidance in Polynomial Product Codes

Product codes are a concatenated error-correction scheme that has been often considered for applications requiring very low bit-error rates, which demand that the error floor be decreased as much as possible. In this work, we consider product codes constructed from polynomial algebraic codes, and propose a novel low-complexity post-processing technique that is able to improve the error-correction performance by orders of magnitude. We provide lower bounds for the error rate achievable under post processing, and present simulation results indicating that these bounds are tight.Comment: 4 pages, 2 figures, GlobalSiP 201

A Review :Implementation of Reed Solomon Error Correction & Detec-tion For Wireless Network 802.16

The reed Solomon (255,239) are error-correcting & detecting code. Reed-Solomon codes are the most frequently used digital error control. It is also called as forword error code. The main part of reed-Solomon encoder is the linear feedback shift register that is implemented using VHDL A pipelined RS decoders is proposed of reducing the hardware complexity use the pipelined GFmultiplier in the syndrome computation block, KES block, Forney block, Chien search block and error correction block for provides low com-plexity the extended inversion less Massey-Berlekamp algorithm is used. The extended inversion less Massey-Berlekamp algorithm overcomes both the error locator polynomial and the error evaluator polynomial at the same time

Frequency Diversity Performance of Coded Multiband-OFDM Systems on IEEE UWB Channels

This paper investigates how convolutional and Reed-Solomon codes can be used to improve the performance of multiband-OFDM by utilizing the inherent frequency diversity of the new IEEE 802.15 UWB channel models. A normalized amplitude autocovariance function of the Fourier transform of the channel impulse response is defined. Then the average coherence bandwidths of CM1, CM2, CM3, and CM4 are estimated to be 31.6, 16.3, 11.0, 5.8 MHz, respectively. Using the central limit theorem, we can expect that the performance of an uncoded OFDM system on CM1-CM4 without shadowing is the same as in a Rayleigh fading channel with uniformly distributed phase. The performance of a convolutional code with rate 1/2 and constraint length 7 on CM2-CM4 without shadowing are up to 0.4 dB worse than that of on an uncorrelated Rayleigh fading channel. The loss for CM1 is around 1 dB. A block interleaver with 32 rows and 24 columns was used. This result is also valid for a convolutional code with rate 1/4 and constraint length 7. For code rates around 2/3, the performance of a punctured convolutional code with soft-decision decoding is much better than that of the Reed-Solomon codes with with 6, 7, and 8 bits per symbol and hard-decision decoding

Architectures for soft-decision decoding of non-binary codes

En esta tesis se estudia el dise¿no de decodificadores no-binarios para la correcci'on de errores en sistemas de comunicaci'on modernos de alta velocidad. El objetivo es proponer soluciones de baja complejidad para los algoritmos de decodificaci'on basados en los c'odigos de comprobaci'on de paridad de baja densidad no-binarios (NB-LDPC) y en los c'odigos Reed-Solomon, con la finalidad de implementar arquitecturas hardware eficientes. En la primera parte de la tesis se analizan los cuellos de botella existentes en los algoritmos y en las arquitecturas de decodificadores NB-LDPC y se proponen soluciones de baja complejidad y de alta velocidad basadas en el volteo de s'¿mbolos. En primer lugar, se estudian las soluciones basadas en actualizaci'on por inundaci 'on con el objetivo de obtener la mayor velocidad posible sin tener en cuenta la ganancia de codificaci'on. Se proponen dos decodificadores diferentes basados en clipping y t'ecnicas de bloqueo, sin embargo, la frecuencia m'axima est'a limitada debido a un exceso de cableado. Por este motivo, se exploran algunos m'etodos para reducir los problemas de rutado en c'odigos NB-LDPC. Como soluci'on se propone una arquitectura basada en difusi'on parcial para algoritmos de volteo de s'¿mbolos que mitiga la congesti'on por rutado. Como las soluciones de actualizaci 'on por inundaci'on de mayor velocidad son sub-'optimas desde el punto de vista de capacidad de correci'on, decidimos dise¿nar soluciones para la actualizaci'on serie, con el objetivo de alcanzar una mayor velocidad manteniendo la ganancia de codificaci'on de los algoritmos originales de volteo de s'¿mbolo. Se presentan dos algoritmos y arquitecturas de actualizaci'on serie, reduciendo el 'area y aumentando de la velocidad m'axima alcanzable. Por 'ultimo, se generalizan los algoritmos de volteo de s'¿mbolo y se muestra como algunos casos particulares puede lograr una ganancia de codificaci'on cercana a los algoritmos Min-sum y Min-max con una menor complejidad. Tambi'en se propone una arquitectura eficiente, que muestra que el 'area se reduce a la mitad en comparaci'on con una soluci'on de mapeo directo. En la segunda parte de la tesis, se comparan algoritmos de decodificaci'on Reed- Solomon basados en decisi'on blanda, concluyendo que el algoritmo de baja complejidad Chase (LCC) es la soluci'on m'as eficiente si la alta velocidad es el objetivo principal. Sin embargo, los esquemas LCC se basan en la interpolaci'on, que introduce algunas limitaciones hardware debido a su complejidad. Con el fin de reducir la complejidad sin modificar la capacidad de correcci'on, se propone un esquema de decisi'on blanda para LCC basado en algoritmos de decisi'on dura. Por 'ultimo se dise¿na una arquitectura eficiente para este nuevo esquemaGarcía Herrero, FM. (2013). Architectures for soft-decision decoding of non-binary codes [Tesis doctoral no publicada]. Universitat Politècnica de València. https://doi.org/10.4995/Thesis/10251/33753TESISPremiad

Reed-Solomon turbo product codes for optical communications: from code optimization to decoder design

International audienceTurbo product codes (TPCs) are an attractive solution to improve link budgets and reduce systems costs by relaxing the requirements on expensive optical devices in high capacity optical transport systems. In this paper, we investigate the use of Reed-Solomon (RS) turbo product codes for 40 Gbps transmission over optical transport networks and 10 Gbps transmission over passive optical networks. An algorithmic study is first performed in order to design RS TPCs that are compatible with the performance requirements imposed by the two applications. Then, a novel ultrahigh-speed parallel architecture for turbo decoding of product codes is described. A comparison with binary Bose-Chaudhuri-Hocquenghem (BCH) TPCs is performed. The results show that high-rate RS TPCs offer a better complexity/performance tradeoff than BCH TPCs for low-cost Gbps fiber optic communications

FEC killed the cut-through switch

Latency penalty in Ethernet links beyond 10Gb/s is due to forward error correction (FEC) blocks. In the worst case a single-hop penalty approaches the latency of an entire cutthrough switch. Latency jitter is also introduced, making latency prediction harder, with large peak to peak variance. These factors stretch the tail of latency distribution in Rackscale systems and Data Centers, which in turn degrades performance of distributed applications. We analyse the underlying mechanisms, calculate lower bounds and propose a different approach that would reduce the penalty, allow control over latency and feedback for application level optimisation.Rudin foundation, Isaac Newton trust, Leverhulme trust, Microsoft researc