An Experimental Proof that Resistance-Switching Memory Cells are not Memristors

It has been suggested that all resistive-switching memory cells are memristors. The latter are hypothetical, ideal devices whose resistance, as originally formulated, depends only on the net charge that traverses them. Recently, an unambiguous test has been proposed [J. Phys. D: Appl. Phys. {\bf 52}, 01LT01 (2019)] to determine whether a given physical system is indeed a memristor or not. Here, we experimentally apply such a test to both in-house fabricated Cu-SiO2 and commercially available electrochemical metallization cells. Our results unambiguously show that electrochemical metallization memory cells are not memristors. Since the particular resistance-switching memories employed in our study share similar features with many other memory cells, our findings refute the claim that all resistance-switching memories are memristors. They also cast doubts on the existence of ideal memristors as actual physical devices that can be fabricated experimentally. Our results then lead us to formulate two memristor impossibility conjectures regarding the impossibility of building a model of physical resistance-switching memories based on the memristor model

Memristors for the Curious Outsiders

We present both an overview and a perspective of recent experimental advances and proposed new approaches to performing computation using memristors. A memristor is a 2-terminal passive component with a dynamic resistance depending on an internal parameter. We provide an brief historical introduction, as well as an overview over the physical mechanism that lead to memristive behavior. This review is meant to guide nonpractitioners in the field of memristive circuits and their connection to machine learning and neural computation.Comment: Perpective paper for MDPI Technologies; 43 page

An experimental demonstration of the memristor test

A simple and unambiguous test has been recently suggested [J. Phys. D: Applied Physics, 52, 01LT01 (2018)] to check experimentally if a resistor with memory is indeed a memristor, namely a resistor whose resistance depends only on the charge that flows through it, or on the history of the voltage across it. However, although such a test would represent the litmus test for claims about memristors (in the ideal sense), it has yet to be applied widely to actual physical devices. In this paper, we experimentally apply it to a current-carrying wire interacting with a magnetic core, which was recently claimed to be a memristor (so-called `$\Phi$ memristor') [J. Appl. Phys. 125, 054504 (2019)]. The results of our experiment demonstrate unambiguously that this `$\Phi$ memristor' is not a memristor: it is simply an inductor with memory. This demonstration casts further doubts that ideal memristors do actually exist in nature or may be easily created in the lab

Experimental study of artificial neural networks using a digital memristor simulator

© 2018 IEEE. Personal use of this material is permitted. Permission from IEEE must be obtained for all other uses, in any current or future media, including reprinting/republishing this material for advertising or promotional purposes,creating new collective works, for resale or redistribution to servers or lists, or reuse of any copyrighted component of this work in other works.This paper presents a fully digital implementation of a memristor hardware simulator, as the core of an emulator, based on a behavioral model of voltage-controlled threshold-type bipolar memristors. Compared to other analog solutions, the proposed digital design is compact, easily reconfigurable, demonstrates very good matching with the mathematical model on which it is based, and complies with all the required features for memristor emulators. We validated its functionality using Altera Quartus II and ModelSim tools targeting low-cost yet powerful field programmable gate array (FPGA) families. We tested its suitability for complex memristive circuits as well as its synapse functioning in artificial neural networks (ANNs), implementing examples of associative memory and unsupervised learning of spatio-temporal correlations in parallel input streams using a simplified STDP. We provide the full circuit schematics of all our digital circuit designs and comment on the required hardware resources and their scaling trends, thus presenting a design framework for applications based on our hardware simulator.Peer ReviewedPostprint (author's final draft