3,064 research outputs found
Modified Level Restorers Using Current Sink and Current Source Inverter Structures for BBL-PT Full Adder
Full adder is an essential component for the design and development of all types of processors like digital signal processors (DSP), microprocessors etc. In most of these systems adder lies in the critical path that affects the overall speed of the system. So enhancing the performance of the 1-bit full adder cell is a significant goal. In this paper, we proposed two modified level restorers using current sink and current source inverter structures for branch-based logic and pass-transistor (BBL-PT) full adder [1]. In BBL-PT full adder, there lies a drawback i.e. voltage step existence that could be eliminated in the proposed logics by using the current sink inverter and current source inverter structures. The proposed full adders are compared with the two standard and well-known logic styles, i.e. conventional static CMOS logic and Complementary Pass transistor Logic (CPL), demonstrated the good delay performance. The implementation of 8-bit ripple carry adder based on proposed full adders are finally demonstrated. The CPL 8-bit RCA and as well as the proposed ones is having better delay performance than the static CMOS and BBL-PT 8-bit RCA. The performance of the proposed BBL-PT cell with current sink & current source inverter structures are examined using PSPICE and the model parameters of a 0.13 µm CMOS process
Design of Adiabatic MTJ-CMOS Hybrid Circuits
Low-power designs are a necessity with the increasing demand of portable
devices which are battery operated. In many of such devices the operational
speed is not as important as battery life. Logic-in-memory structures using
nano-devices and adiabatic designs are two methods to reduce the static and
dynamic power consumption respectively. Magnetic tunnel junction (MTJ) is an
emerging technology which has many advantages when used in logic-in-memory
structures in conjunction with CMOS. In this paper, we introduce a novel
adiabatic hybrid MTJ/CMOS structure which is used to design AND/NAND, XOR/XNOR
and 1-bit full adder circuits. We simulate the designs using HSPICE with 32nm
CMOS technology and compared it with a non-adiabatic hybrid MTJ/CMOS circuits.
The proposed adiabatic MTJ/CMOS full adder design has more than 7 times lower
power consumtion compared to the previous MTJ/CMOS full adder
Non-Volatile Magnonic Logic Circuits Engineering
We propose a concept of magnetic logic circuits engineering, which takes an
advantage of magnetization as a computational state variable and exploits spin
waves for information transmission. The circuits consist of magneto-electric
cells connected via spin wave buses. We present the result of numerical
modeling showing the magneto-electric cell switching as a function of the
amplitude as well as the phase of the spin wave. The phase-dependent switching
makes it possible to engineer logic gates by exploiting spin wave buses as
passive logic elements providing a certain phase-shift to the propagating spin
waves. We present a library of logic gates consisting of magneto-electric cells
and spin wave buses providing 0 or p phase shifts. The utilization of phases in
addition to amplitudes is a powerful tool which let us construct logic circuits
with a fewer number of elements than required for CMOS technology. As an
example, we present the design of the magnonic Full Adder Circuit comprising
only 5 magneto-electric cells. The proposed concept may provide a route to more
functional wave-based logic circuitry with capabilities far beyond the limits
of the traditional transistor-based approach
Energy consumption by reversible circuits in the 130 nm and 65 nm nodes
We show that both 130 nm and 65 nm technologies
are suitable for reversible computation
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