Layout Decomposition for Quadruple Patterning Lithography and Beyond

For next-generation technology nodes, multiple patterning lithography (MPL) has emerged as a key solution, e.g., triple patterning lithography (TPL) for 14/11nm, and quadruple patterning lithography (QPL) for sub-10nm. In this paper, we propose a generic and robust layout decomposition framework for QPL, which can be further extended to handle any general K-patterning lithography (K$>$4). Our framework is based on the semidefinite programming (SDP) formulation with novel coloring encoding. Meanwhile, we propose fast yet effective coloring assignment and achieve significant speedup. To our best knowledge, this is the first work on the general multiple patterning lithography layout decomposition.Comment: DAC'201

A High-Performance Triple Patterning Layout Decomposer with Balanced Density

Triple patterning lithography (TPL) has received more and more attentions from industry as one of the leading candidate for 14nm/11nm nodes. In this paper, we propose a high performance layout decomposer for TPL. Density balancing is seamlessly integrated into all key steps in our TPL layout decomposition, including density-balanced semi-definite programming (SDP), density-based mapping, and density-balanced graph simplification. Our new TPL decomposer can obtain high performance even compared to previous state-of-the-art layout decomposers which are not balanced-density aware, e.g., by Yu et al. (ICCAD'11), Fang et al. (DAC'12), and Kuang et al. (DAC'13). Furthermore, the balanced-density version of our decomposer can provide more balanced density which leads to less edge placement error (EPE), while the conflict and stitch numbers are still very comparable to our non-balanced-density baseline

Extended Micromorphic Computational Homogenization for Mechanical Metamaterials Exhibiting Multiple Geometric Pattern Transformations

Honeycomb-like microstructures have been shown to exhibit local elastic buckling under compression, with three possible geometric buckling modes, or pattern transformations. The individual pattern transformations, and consequently also spatially distributed patterns, can be induced by controlling the applied compression along two orthogonal directions. Exploitation of this property holds great potential in, e.g., soft robotics applications. For fast and optimal design, efficient numerical tools are required, capable of bridging the gap between the microstructural and engineering scale, while capturing all relevant pattern transformations. A micromorphic homogenization framework for materials exhibiting multiple pattern transformations is therefore presented in this paper, which extends the micromorphic scheme of Roko\v{s} et al., J. Mech. Phys. Solids 123, 119-137 (2019), for elastomeric metamaterials exhibiting only a single pattern transformation. The methodology is based on a suitable kinematic ansatz consisting of a smooth part, a set of spatially correlated fluctuating fields, and a remaining, spatially uncorrelated microfluctuation field. Whereas the latter field is neglected or condensed out at the level of each macroscopic material point, the magnitudes of the spatially correlated fluctuating fields emerge at the macroscale as micromorphic fields. We develop the balance equations which these micromorphic fields must satisfy as well as a computational homogenization approach to compute the generalized stresses featuring in these equations. To demonstrate the potential of the methodology, loading cases resulting in mixed modes in both space and time are studied and compared against full-scale simulations. It is shown that the proposed framework is capable of capturing the relevant phenomena, although the inherent multiplicity of solutions entails sensitivity to the initial guess.Comment: 22 pages, 13 figures, Extreme Mechanics Letters, 8 April 202

Coherent electron transport by adiabatic passage in an imperfect donor chain

Coherent Tunneling Adiabatic Passage (CTAP) has been proposed as a long-range physical qubit transport mechanism in solid-state quantum computing architectures. Although the mechanism can be implemented in either a chain of quantum dots or donors, a 1D chain of donors in Si is of particular interest due to the natural confining potential of donors that can in principle help reduce the gate densities in solid-state quantum computing architectures. Using detailed atomistic modeling, we investigate CTAP in a more realistic triple donor system in the presence of inevitable fabrication imperfections. In particular, we investigate how an adiabatic pathway for CTAP is affected by donor misplacements, and propose schemes to correct for such errors. We also investigate the sensitivity of the adiabatic path to gate voltage fluctuations. The tight-binding based atomistic treatment of straggle used here may benefit understanding of other donor nanostructures, such as donor-based charge and spin qubits. Finally, we derive an effective 3 \times 3 model of CTAP that accurately resembles the voltage tuned lowest energy states of the multi-million atom tight-binding simulations, and provides a translation between intensive atomistic Hamiltonians and simplified effective Hamiltonians while retaining the relevant atomic-scale information. This method can help characterize multi-donor experimental structures quickly and accurately even in the presence of imperfections, overcoming some of the numeric intractabilities of finding optimal eigenstates for non-ideal donor placements.Comment: 9 pages, 8 figure

Layout decomposition for triple patterning lithography

Nowadays the semiconductor industry is continuing to advance the limits of physics as the feature size of the chip keeps shrinking. Products of the 22 nm technology node are already available on the market, and there are many ongoing research studies for the 14/10 nm technology nodes and beyond. Due to the physical limitations, the traditional 193 nm immersion lithography is facing huge challenges in fabricating such tiny features. Several types of next-generation lithography techniques have been discussed for years, such as {\em extreme ultra-violet} (EUV) lithography, {\em E-beam direct write}, and {\em block copolymer directed self-assembly} (DSA). However, the source power for EUV is still an unresolved issue. The low throughput of E-beam makes it impractical for massive productions. DSA is still under calibration in research labs and is not ready for massive industrial deployment. Traditionally features are fabricated under single litho exposure. As feature size becomes smaller and smaller, single exposure is no longer adequate in satisfying the quality requirements. {\em Double patterning lithography} (DPL) utilizes two litho exposures to manufacture features on the same layer. Features are assigned to two masks, with each mask going through a separate litho exposure. With one more mask, the effective pitch is doubled, thus greatly enhancing the printing resolution. Therefore, DPL has been widely recognized as a feasible lithography solution in the sub-22 nm technology node. However, as the technology continues to scale down to 14/10 nm and beyond, DPL begins to show its limitations as it introduces a high number of stitches, which increases the manufacturing cost and potentially leads to functional errors of the circuits. {\em Triple pattering lithography} (TPL) uses three masks to print the features on the same layer, which further enhances the printing resolution. It is a natural extension for DPL with three masks available, and it is one of the most promising solutions for the 14/10 nm technology node and beyond. In this thesis, TPL decomposition for standard-cell-based designs is extensively studied. We proposed a polynomial time triple patterning decomposition algorithm which guarantees finding a TPL decomposition if one exists. For complex designs with stitch candidates, our algorithm is able to find a solution with the optimal number of stitches. For standard-cell-based designs, there are additional coloring constraints where the same type of cell should be fabricated following the same pattern. We proposed an algorithm that is guaranteed to find a solution when one exists. The framework of the algorithm is also extended to pattern-based TPL decompositions, where the cost of a decomposition can be minimized given a library of different patterns. The polynomial time TPL algorithm is further optimized in terms of runtime and memory while keeping the solution quality unaffected. We also studied the TPL aware detailed placement problem, where our approach is guaranteed to find a legal detailed placement satisfying TPL coloring constraints as well as minimizing the {\em half-perimeter wire length} (HPWL). Finally, we studied the problem of performance variations due to mask misalignment in {\em multiple patterning decompositions} (MPL). For advanced technology nodes, process variations (mainly mask misalignment) have significant influences on the quality of fabricated circuits, and often lead to unexpected power/timing degenerations. Mask misalignment would complicate the way of simulating timing closure if engineers do not understand the underlying effects of mask misalignment, which only exists in multiple patterning decompositions. We mathematically proved the worst-case scenarios of coupling capacitance incurred by mask misalignment in MPL decompositions. A graph model is proposed which is guaranteed to compute the tight upper bound on the worst-case coupling capacitance of any MPL decompositions for a given layout